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-- VHDL data flow description generated from `ofb`

--              date : Sat Sep  1 20:13:14 2001

-- Entity Declaration

ENTITY ofb IS

  PORT (

  active : in BIT;      -- active

  clk : in BIT; -- clk

  key_ready : in BIT;   -- key_ready

  dt_ready : in BIT;    -- dt_ready

  finish : in BIT;      -- finish

  first_dt : inout BIT; -- first_dt

  e_mesin : out BIT;    -- e_mesin

  s_mesin : out BIT;    -- s_mesin

  emp_buf : out BIT;    -- emp_buf

  cp_ready : out BIT;   -- cp_ready

  cke_b_mode : out BIT; -- cke_b_mode

  en_in : out BIT;      -- en_in

  en_iv : out BIT;      -- en_iv

  en_rcbc : out BIT;    -- en_rcbc

  en_out : out BIT;     -- en_out

  sel1 : out bit_vector(1 DOWNTO 0) ;   -- sel1

  sel2 : out bit_vector(1 DOWNTO 0) ;   -- sel2

  sel3 : out bit_vector(1 DOWNTO 0) ;   -- sel3

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END ofb;

-- Architecture Declaration

ARCHITECTURE VBE OF ofb IS

  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL current_state_s13 : BIT;               -- current_state_s13

  SIGNAL next_state_s13 : BIT;          -- next_state_s13

  SIGNAL current_state_s12 : BIT;               -- current_state_s12

  SIGNAL next_state_s12 : BIT;          -- next_state_s12

  SIGNAL current_state_s11 : BIT;               -- current_state_s11

  SIGNAL next_state_s11 : BIT;          -- next_state_s11

  SIGNAL current_state_s10 : BIT;               -- current_state_s10

  SIGNAL next_state_s10 : BIT;          -- next_state_s10

  SIGNAL current_state_s9 : BIT;                -- current_state_s9

  SIGNAL next_state_s9 : BIT;           -- next_state_s9

  SIGNAL current_state_s8 : BIT;                -- current_state_s8

  SIGNAL next_state_s8 : BIT;           -- next_state_s8

  SIGNAL current_state_s7 : BIT;                -- current_state_s7

  SIGNAL next_state_s7 : BIT;           -- next_state_s7

  SIGNAL current_state_s6 : BIT;                -- current_state_s6

  SIGNAL next_state_s6 : BIT;           -- next_state_s6

  SIGNAL current_state_s5 : BIT;                -- current_state_s5

  SIGNAL next_state_s5 : BIT;           -- next_state_s5

  SIGNAL current_state_s4 : BIT;                -- current_state_s4

  SIGNAL next_state_s4 : BIT;           -- next_state_s4

  SIGNAL current_state_s3 : BIT;                -- current_state_s3

  SIGNAL next_state_s3 : BIT;           -- next_state_s3

  SIGNAL current_state_s2 : BIT;                -- current_state_s2

  SIGNAL next_state_s2 : BIT;           -- next_state_s2

  SIGNAL current_state_s1 : BIT;                -- current_state_s1

  SIGNAL next_state_s1 : BIT;           -- next_state_s1

  SIGNAL current_state_s0 : BIT;                -- current_state_s0

  SIGNAL next_state_s0 : BIT;           -- next_state_s0

  SIGNAL next_state : BIT_VECTOR(3 DOWNTO 0);   -- next_state

BEGIN

  next_state(0) <= (next_state_s3 OR next_state_s6 OR next_state_s7

OR next_state_s9 OR next_state_s10 OR

next_state_s12 OR next_state_s13);

  next_state(1) <= (next_state_s0 OR next_state_s2 OR next_state_s3

OR next_state_s10 OR next_state_s11 OR

next_state_s12 OR next_state_s13);

  next_state(2) <= (next_state_s0 OR next_state_s4 OR next_state_s5

OR next_state_s6 OR next_state_s9 OR next_state_s10

 OR next_state_s11 OR next_state_s13);

  next_state(3) <= (next_state_s4 OR next_state_s8 OR next_state_s9

OR next_state_s11 OR next_state_s12 OR

next_state_s13);

  next_state_s0 <= '0';

  current_state_s0 <= (NOT(current_state(3)) AND current_state(2) AND

current_state(1) AND NOT(current_state(0)));

  next_state_s1 <= (current_state_s0 OR (current_state_s1 AND (NOT(

dt_ready) OR NOT(key_ready))));

  current_state_s1 <= (NOT(current_state(3)) AND NOT(current_state(2))

AND NOT(current_state(1)) AND NOT(current_state(0)));

  next_state_s2 <= (current_state_s1 AND dt_ready AND first_dt AND

key_ready);

  current_state_s2 <= (NOT(current_state(2)) AND current_state(1) AND

NOT(current_state(0)));

  next_state_s3 <= current_state_s2;

  current_state_s3 <= (NOT(current_state(3)) AND NOT(current_state(2))

AND current_state(1) AND current_state(0));

  next_state_s4 <= current_state_s3;

  current_state_s4 <= (current_state(3) AND current_state(2) AND NOT(

current_state(1)) AND NOT(current_state(0)));

  next_state_s5 <= (current_state_s1 AND dt_ready AND NOT(first_dt)

AND key_ready);

  current_state_s5 <= (NOT(current_state(3)) AND current_state(2) AND

NOT(current_state(1)) AND NOT(current_state(0)));

  next_state_s6 <= (current_state_s4 OR current_state_s5);

  current_state_s6 <= (NOT(current_state(3)) AND current_state(2) AND

NOT(current_state(1)) AND current_state(0));

  next_state_s7 <= (current_state_s6 OR (current_state_s7 AND (NOT(

dt_ready) OR NOT(finish))));

  current_state_s7 <= (NOT(current_state(2)) AND NOT(current_state(1))

AND current_state(0));

  next_state_s8 <= (current_state_s7 AND dt_ready AND finish);

  current_state_s8 <= (current_state(3) AND NOT(current_state(2)) AND

NOT(current_state(1)));

  next_state_s9 <= current_state_s8;

  current_state_s9 <= (current_state(3) AND NOT(current_state(1)) AND

current_state(0));

  next_state_s10 <= current_state_s9;

  current_state_s10 <= (NOT(current_state(3)) AND current_state(2) AND

current_state(1) AND current_state(0));

  next_state_s11 <= current_state_s10;

  current_state_s11 <= (current_state(3) AND current_state(1) AND NOT(

current_state(0)));

  next_state_s12 <= current_state_s11;

  current_state_s12 <= (current_state(3) AND NOT(current_state(2)) AND

current_state(1));

  next_state_s13 <= (current_state_s12 OR current_state_s13);

  current_state_s13 <= (current_state(3) AND current_state(2) AND

current_state(1) AND current_state(0));

  label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')

  BEGIN

    current_state(0) <= GUARDED (next_state(0) AND NOT(active));

  END BLOCK label0;

  label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')

  BEGIN

    current_state(1) <= GUARDED (next_state(1) OR active);

  END BLOCK label1;

  label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')

  BEGIN

    current_state(2) <= GUARDED (next_state(2) OR active);

  END BLOCK label2;

  label3 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')

  BEGIN

    current_state(3) <= GUARDED (next_state(3) AND NOT(active));

  END BLOCK label3;

sel3(0) <= ((current_state_s1 AND dt_ready AND NOT(first_dt)

 AND key_ready AND NOT(active)) OR (

current_state_s9 AND NOT(active)) OR (current_state_s10 AND NOT(

active)) OR (current_state_s11 AND NOT(active)) OR (

current_state_s12 AND NOT(active)) OR (current_state_s13 AND NOT(

active)));

sel3(1) <= NOT((current_state_s1 AND dt_ready AND NOT(

first_dt) AND key_ready AND NOT(active)) OR (

current_state_s9 AND NOT(active)) OR (current_state_s10 AND NOT(

active)) OR (current_state_s11 AND NOT(active)) OR (

current_state_s12 AND NOT(active)) OR (current_state_s13 AND NOT(

active)));

sel2(0) <= ((current_state_s1 AND dt_ready AND NOT(first_dt)

 AND key_ready AND NOT(active)) OR (

current_state_s3 AND NOT(active)));

sel2(1) <= NOT((current_state_s1 AND dt_ready AND NOT(

first_dt) AND key_ready AND NOT(active)) OR (

current_state_s3 AND NOT(active)));

sel1(0) <= ((current_state_s1 AND dt_ready AND first_dt AND

key_ready AND NOT(active)) OR (current_state_s2 AND NOT(

active)));

sel1(1) <= NOT((current_state_s1 AND dt_ready AND first_dt

AND key_ready AND NOT(active)) OR (current_state_s2

AND NOT(active)) OR (current_state_s7 AND dt_ready

AND finish AND NOT(active)) OR (current_state_s8 AND

 NOT(active)));

en_out <= (current_state_s10 AND NOT(active));

en_rcbc <= '0';

en_iv <= ((current_state_s2 AND NOT(active)) OR (

current_state_s8 AND NOT(active)));

en_in <= ((current_state_s1 AND dt_ready AND first_dt AND

key_ready AND NOT(active)) OR (current_state_s7 AND

dt_ready AND finish AND NOT(active)) OR (current_state_s8

 AND NOT(active)));

cke_b_mode <= NOT(active);

cp_ready <= (current_state_s11 AND NOT(active));

emp_buf <= ((current_state_s1 AND dt_ready AND first_dt AND

key_ready AND NOT(active)) OR (current_state_s7 AND

dt_ready AND finish AND NOT(active)) OR (current_state_s8

 AND NOT(active)));

s_mesin <= ((current_state_s4 AND NOT(active)) OR (

current_state_s5 AND NOT(active)) OR (current_state_s6 AND NOT(

active)) OR (current_state_s7 AND (NOT(dt_ready) OR NOT

(finish)) AND NOT(active)));

e_mesin <= '1';

first_dt <= (active OR (current_state_s0 AND NOT(active)) OR

(current_state_s1 AND NOT(active)));

END;