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--

-- Generated by VASY

--

ENTITY reg1 IS

PORT(

  en    : IN BIT;

  clr   : IN BIT;

  cke   : IN BIT;

  a     : IN BIT;

  b     : OUT BIT

);

END reg1;

ARCHITECTURE VBE OF reg1 IS

  SIGNAL c_0    : REG_BIT REGISTER;

BEGIN

  LABEL0 : BLOCK (clr)

  BEGIN

    c_0 <= GUARDED '0';

  END BLOCK LABEL0;

  LABEL1 : BLOCK  (clr = '0' AND en = '1')

  BEGIN

    c_0 <= GUARDED a WHEN cke ELSE c_0;

  END BLOCK LABEL1;

  b <= c_0;

END VBE;