URL https://opencores.org/ocsvn/idea/idea/trunk

Subversion Repositories idea

[/] [idea/] [trunk/] [fsm/] [control_datain.fsm] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log


-- File Name   : control_datain.fsm                             --
-- Description : The control of data-in blok                    --
-- Purpose     : To be used by SYF                              --
-- Date        : Aug 30, 2001                                   --
-- Version     : 1.1                                            --
-- Author      : Martadinata A.                                 --
-- Address     : VLSI RG, Dept. of Electrical Engineering ITB,  --
--               Bandung, Indonesia                             --
-- E-mail      : marta@ic.vlsi.itb.ac.id                        --
 
ENTITY control_datain IS
PORT ( clk,rst,dt_sended,emp_buf    : IN  BIT;
       en_bufin,req_dt,dt_ready     : OUT BIT;
       n_block                      : OUT BIT;
       vdd, vss                     : IN BIT
      );
END control_datain;
 
ARCHITECTURE fsm OF control_datain IS
 
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4);
 
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
 
SIGNAL CURRENT_STATE, NEXT_STATE: STATE_TYPE;
 
BEGIN
  PROCESS ( CURRENT_STATE, rst, emp_buf)
    BEGIN
      IF ( rst = '1' ) THEN
          NEXT_STATE <= S0;
          req_dt <= '1';
          en_bufin <= '0';
          dt_ready <= '0';
          n_block  <= '0';
      ELSE
          CASE CURRENT_STATE IS
             WHEN S0 =>
                if(dt_sended = '1') then
                   req_dt   <= '0';
                   en_bufin <= '1';
                   dt_ready <= '0';
                   n_block  <= '0';
                   NEXT_STATE <= S1;
                 else
                   req_dt   <= '1';
                   en_bufin <= '0';
                   dt_ready <= '0';
                   n_block  <= '0';
                   NEXT_STATE <= S0;
                 end if;
             WHEN S1 =>
                   req_dt   <= '1';
                   en_bufin <= '0';
                   dt_ready <= '0';
                   n_block  <= '1';
                   NEXT_STATE <= S2;
             WHEN S2 =>
                if(dt_sended = '1') then
                   req_dt   <= '0';
                   en_bufin <= '1';
                   dt_ready <= '0';
                   n_block  <= '1';
                   NEXT_STATE <= S3;
                else
                   req_dt   <= '1';
                   en_bufin <= '0';
                   dt_ready <= '0';
                   n_block  <= '1';
                   NEXT_STATE <= S2;
                end if;
             WHEN S3 =>
                   req_dt   <= '0';
                   en_bufin <= '0';
                   dt_ready <= '1';
                   n_block  <= '0';
                   NEXT_STATE <= S4;
             WHEN S4 =>
                if(emp_buf = '1') then
                   req_dt   <= '1';
                   en_bufin <= '0';
                   dt_ready <= '0';
                   n_block  <= '0';
                   NEXT_STATE <= S0;
                else
                   req_dt   <= '0';
                   en_bufin <= '0';
                   dt_ready <= '1';
                   n_block  <= '0';
                   NEXT_STATE <= S4;
                end if;
             WHEN OTHERS =>
                ASSERT ( '1' )
                REPORT "Illegal State";
 
          END CASE;
      END IF;
END PROCESS;
 
PROCESS (clk)
  BEGIN
    IF ((clk AND NOT clk'STABLE) ='1') THEN
         CURRENT_STATE <= NEXT_STATE;
    END IF;
END PROCESS;
 
END fsm;

Line No.	Rev	Author	Line
1	5	marta	`-- File Name : control_datain.fsm --`
2			`-- Description : The control of data-in blok --`
3			`-- Purpose : To be used by SYF --`
4			`-- Date : Aug 30, 2001 --`
5			`-- Version : 1.1 --`
6			`-- Author : Martadinata A. --`
7			`-- Address : VLSI RG, Dept. of Electrical Engineering ITB, --`
8			`-- Bandung, Indonesia --`
9			`-- E-mail : marta@ic.vlsi.itb.ac.id --`
10
11			`ENTITY control_datain IS`
12			`PORT ( clk,rst,dt_sended,emp_buf : IN BIT;`
13			`en_bufin,req_dt,dt_ready : OUT BIT;`
14			`n_block : OUT BIT;`
15			`vdd, vss : IN BIT`
16			`);`
17			`END control_datain;`
18
19			`ARCHITECTURE fsm OF control_datain IS`
20
21			`TYPE STATE_TYPE IS (S0, S1, S2, S3, S4);`
22
23			`-- pragma CLOCK clk`
24			`-- pragma CURRENT_STATE CURRENT_STATE`
25			`-- pragma NEXT_STATE NEXT_STATE`
26
27			`SIGNAL CURRENT_STATE, NEXT_STATE: STATE_TYPE;`
28
29			`BEGIN`
30			`PROCESS ( CURRENT_STATE, rst, emp_buf)`
31			`BEGIN`
32			`IF ( rst = '1' ) THEN`
33			`NEXT_STATE <= S0;`
34			`req_dt <= '1';`
35			`en_bufin <= '0';`
36			`dt_ready <= '0';`
37			`n_block <= '0';`
38			`ELSE`
39			`CASE CURRENT_STATE IS`
40			`WHEN S0 =>`
41			`if(dt_sended = '1') then`
42			`req_dt <= '0';`
43			`en_bufin <= '1';`
44			`dt_ready <= '0';`
45			`n_block <= '0';`
46			`NEXT_STATE <= S1;`
47			`else`
48			`req_dt <= '1';`
49			`en_bufin <= '0';`
50			`dt_ready <= '0';`
51			`n_block <= '0';`
52			`NEXT_STATE <= S0;`
53			`end if;`
54			`WHEN S1 =>`
55			`req_dt <= '1';`
56			`en_bufin <= '0';`
57			`dt_ready <= '0';`
58			`n_block <= '1';`
59			`NEXT_STATE <= S2;`
60			`WHEN S2 =>`
61			`if(dt_sended = '1') then`
62			`req_dt <= '0';`
63			`en_bufin <= '1';`
64			`dt_ready <= '0';`
65			`n_block <= '1';`
66			`NEXT_STATE <= S3;`
67			`else`
68			`req_dt <= '1';`
69			`en_bufin <= '0';`
70			`dt_ready <= '0';`
71			`n_block <= '1';`
72			`NEXT_STATE <= S2;`
73			`end if;`
74			`WHEN S3 =>`
75			`req_dt <= '0';`
76			`en_bufin <= '0';`
77			`dt_ready <= '1';`
78			`n_block <= '0';`
79			`NEXT_STATE <= S4;`
80			`WHEN S4 =>`
81			`if(emp_buf = '1') then`
82			`req_dt <= '1';`
83			`en_bufin <= '0';`
84			`dt_ready <= '0';`
85			`n_block <= '0';`
86			`NEXT_STATE <= S0;`
87			`else`
88			`req_dt <= '0';`
89			`en_bufin <= '0';`
90			`dt_ready <= '1';`
91			`n_block <= '0';`
92			`NEXT_STATE <= S4;`
93			`end if;`
94			`WHEN OTHERS =>`
95			`ASSERT ( '1' )`
96			`REPORT "Illegal State";`
97
98			`END CASE;`
99			`END IF;`
100			`END PROCESS;`
101
102			`PROCESS (clk)`
103			`BEGIN`
104			`IF ((clk AND NOT clk'STABLE) ='1') THEN`
105			`CURRENT_STATE <= NEXT_STATE;`
106			`END IF;`
107			`END PROCESS;`
108
109			`END fsm;`

Browse

Tools

Subversion Repositories idea

[/] [idea/] [trunk/] [fsm/] [control_datain.fsm] - Blame information for rev 10