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--Nama file : count3x.fsm

--Deskripsi : counter 3 bit

--Author    : Mas Adit

--Tanggal  : 31 Agustus 2001

entity count3x is

port (

        clk : in bit;

        rst : in bit;

       q : out bit_vector(2 downto 0);

       vdd : in bit;

       vss : in bit

      );

end count3x;

architecture STATE_MACHINE of count3x is

type STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7);

-- pragma CLOCK clk

-- pragma CURRENT_STATE CURRENT_STATE

-- pragma NEXT_STATE NEXT_STATE

signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;

begin

  process ( CURRENT_STATE, rst )

    begin

      if ( rst = '1' ) then

          NEXT_STATE <= S0;

          q <= "000";

      else

          case CURRENT_STATE IS

             when S0 =>

                q <= "000";

                NEXT_STATE <= S1;

             when S1 =>

                q <= "001";

                NEXT_STATE <= S2;

             when S2 =>

                q <= "010";

                NEXT_STATE <= S3;

             when S3 =>

                q <= "011";

                NEXT_STATE <= S4;

             when S4 =>

                q <= "100";

                NEXT_STATE <= S5;

             when S5 =>

                q <= "101";

                NEXT_STATE <= S6;

             when S6 =>

                q <= "110";

                NEXT_STATE <= S7;

             when S7 =>

                q <= "111";

                NEXT_STATE <= S0;

             when OTHERS =>

                assert ( '1' )

                report "Illegal State";

          end case;

      end if;

end process;

process (clk)

  begin

    if ((clk = '1') and not (clk'STABLE)) then

         CURRENT_STATE <= NEXT_STATE;

    end if;

end process;

end STATE_MACHINE;