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[/] [idea/] [trunk/] [fsm/] [key_regulator/] [count4x.fsm] - Blame information for rev 10

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1 6 marta
--Nama file : count4x.fsm
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--Deskripsi : counter 4 bit
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--Author    : Mas Adit
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--Tanggal  : 31 Agustus 2001
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entity count4x is
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port (
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        clk : in bit;
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        rst : in bit;
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       q : out bit_vector(3 downto 0);
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       vdd : in bit;
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       vss : in bit
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      );
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end count4x;
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architecture STATE_MACHINE of count4x is
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type STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15);
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-- pragma CLOCK clk
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-- pragma CURRENT_STATE CURRENT_STATE
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-- pragma NEXT_STATE NEXT_STATE
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signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
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begin
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  process ( CURRENT_STATE, rst )
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    begin
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      if ( rst = '1' ) then
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          NEXT_STATE <= S0;
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          q <= "0000";
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      else
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          case CURRENT_STATE IS
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             when S0 =>
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                q <= "0000";
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                NEXT_STATE <= S1;
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         when S1 =>
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                q <= "0001";
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                NEXT_STATE <= S2;
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             when S2 =>
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                q <= "0010";
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                NEXT_STATE <= S3;
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         when S3 =>
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                q <= "0011";
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                NEXT_STATE <= S4;
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             when S4 =>
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                q <= "0100";
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                NEXT_STATE <= S5;
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             when S5 =>
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                q <= "0101";
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                NEXT_STATE <= S6;
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             when S6 =>
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                q <= "0110";
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                NEXT_STATE <= S7;
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             when S7 =>
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                q <= "0111";
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                NEXT_STATE <= S8;
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             when S8 =>
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                q <= "1000";
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                NEXT_STATE <= S9;
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             when S9 =>
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                q <= "1001";
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                NEXT_STATE <= S10;
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             when S10 =>
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                q <= "1010";
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                NEXT_STATE <= S11;
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         when S11 =>
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                q <= "1011";
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                NEXT_STATE <= S12;
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         when S12 =>
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                q <= "1100";
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                NEXT_STATE <= S13;
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         when S13 =>
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                q <= "1101";
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                NEXT_STATE <= S14;
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             when S14 =>
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                q <= "1110";
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                NEXT_STATE <= S15;
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             when S15 =>
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                q <= "1111";
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                NEXT_STATE <= S0;
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             when OTHERS =>
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                assert ( '1' )
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                report "Illegal State";
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          end case;
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      end if;
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end process;
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process (clk)
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  begin
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    if ((clk = '1') and not (clk'STABLE)) then
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         CURRENT_STATE <= NEXT_STATE;
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    end if;
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end process;
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end STATE_MACHINE;

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