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[/] [idea/] [trunk/] [fsm/] [key_regulator/] [ctr_enkeyx.fsm] - Blame information for rev 6

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--Nama file : ctr_enkeyx.fsm
--Deskripsi : blok kontroller kunci enkripsi
--Author    : Mas Adit
--Tanggal  : 21 Agustus 2001
 
entity ctr_enkeyx is
port (
        clk          : in bit;
        rst          : in bit;
        start        : in bit;
        count      : in bit_vector(2 downto 0);
        en_shft    : out bit;
        en_count : out bit;
        sel1        : out bit;
        sel2        : out bit;
        c_count  : out bit;
        finish      : out bit;
        en_out    : out bit;
        vdd        : in bit;
        vss        : in bit
);
end ctr_enkeyx;
 
architecture STATE_MACHINE of ctr_enkeyx is
 
type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10);
 
        --pragma CLOCK clk
        --pragma CURRENT_STATE CURRENT_STATE
        --pragma NEXT_STATE NEXT_STATE
 
signal  CURRENT_STATE, NEXT_STATE : STATE_TYPE;
 
begin
process (CURRENT_STATE, rst, start, count)
        begin
        if rst then
                NEXT_STATE <= S0;
                en_shft <= '0';
                en_count <= '0';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '0';
                c_count <= '0';
                finish <= '0';
        else
                case CURRENT_STATE is
                when S0 =>
                if start then
                        if (count = "000") then
                                NEXT_STATE <= S1;
                                en_shft <= '0';
                                en_count <= '1';
                                en_out <= '1';
                                sel1 <= '0';
                                sel2 <= '1';
                                c_count <= '0';
                                finish <= '0';
 
                        else
                                if (count = "001") then
                                        NEXT_STATE <= S3;
                                        en_shft <= '1';
                                        en_count <= '1';
                                        en_out <= '0';
                                        sel1 <= '0';
                                        sel2 <= '1';
                                        c_count <= '0';
                                        finish <= '0';
 
                                else
                                        if (count = "111") then
                                                NEXT_STATE <= S10;
                                                en_shft <= '0';
                                                en_count <= '0';
                                                en_out <= '0';
                                                sel1 <= '0';
                                                sel2 <= '0';
                                                c_count <= '0';
                                                finish <= '1';
 
                                        else
                                                NEXT_STATE <= S6;
                                                en_shft <= '0';
                                                en_count <= '0';
                                                en_out <= '0';
                                                sel1 <= '0';
                                                sel2 <= '0';
                                                c_count <= '0';
                                                finish <= '0';
 
                                        end if;
                                end if;
                        end if;
 
                else
                        NEXT_STATE <= S0;
                        en_shft <= '0';
                        en_count <= '0';
                        en_out <= '0';
                        sel1 <= '0';
                        sel2 <= '0';
                        c_count <= '0';
                        finish <= '0';
 
                end if;
 
                when S1 =>
                NEXT_STATE <= S2;
                en_shft <= '0';
                en_count <= '1';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '1';
                finish <= '0';
 
                when  S2 =>
                NEXT_STATE <= S2;
                en_shft <= '0';
                en_count <= '1';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '1';
                finish <= '0';
 
                when S3 =>
                NEXT_STATE <= S4;
                en_shft <= '0';
                en_count <= '1';
                en_out <= '1';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '0';
                finish <= '0';
 
                when S4 =>
                NEXT_STATE <= S5;
                en_shft <= '0';
                en_count <= '1';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '1';
                finish <= '0';
 
                when S5 =>
                NEXT_STATE <= S5;
                en_shft <= '0';
                en_count <= '1';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '1';
                finish <= '0';
 
                when S6 =>
                NEXT_STATE <= S7;
                en_shft <= '1';
                en_count <= '1';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '0';
                finish <= '0';
 
                when S7 =>
                NEXT_STATE <= S8;
                en_shft <= '0';
                en_count <= '1';
                en_out <= '1';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '0';
                finish <= '0';
 
                when S8 =>
                NEXT_STATE <= S9;
                en_shft <= '0';
                en_count <= '1';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '1';
                finish <= '0';
 
                when S9 =>
                NEXT_STATE <= S9;
                en_shft <= '0';
                en_count <= '1';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '1';
                c_count <= '1';
                finish <= '0';
 
                when S10 =>
                NEXT_STATE <= S10;
                en_shft <= '0';
                en_count <= '0';
                en_out <= '0';
                sel1 <= '0';
                sel2 <= '0';
                c_count <= '0';
                finish <= '1';
 
                end case;
        end if;
end process;
 
process (clk)
        begin
        if ((clk = '0') and not(clk'STABLE)) then
                CURRENT_STATE <= NEXT_STATE;
        end if;
end process;
 
end STATE_MACHINE;
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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[/] [idea/] [trunk/] [fsm/] [key_regulator/] [ctr_enkeyx.fsm] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	marta	`--Nama file : ctr_enkeyx.fsm`
2			`--Deskripsi : blok kontroller kunci enkripsi`
3			`--Author : Mas Adit`
4			`--Tanggal : 21 Agustus 2001`
5
6			`entity ctr_enkeyx is`
7			`port (`
8			`clk : in bit;`
9			`rst : in bit;`
10			`start : in bit;`
11			`count : in bit_vector(2 downto 0);`
12			`en_shft : out bit;`
13			`en_count : out bit;`
14			`sel1 : out bit;`
15			`sel2 : out bit;`
16			`c_count : out bit;`
17			`finish : out bit;`
18			`en_out : out bit;`
19			`vdd : in bit;`
20			`vss : in bit`
21			`);`
22			`end ctr_enkeyx;`
23
24			`architecture STATE_MACHINE of ctr_enkeyx is`
25
26			`type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10);`
27
28			`--pragma CLOCK clk`
29			`--pragma CURRENT_STATE CURRENT_STATE`
30			`--pragma NEXT_STATE NEXT_STATE`
31
32			`signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;`
33
34			`begin`
35			`process (CURRENT_STATE, rst, start, count)`
36			`begin`
37			`if rst then`
38			`NEXT_STATE <= S0;`
39			`en_shft <= '0';`
40			`en_count <= '0';`
41			`en_out <= '0';`
42			`sel1 <= '0';`
43			`sel2 <= '0';`
44			`c_count <= '0';`
45			`finish <= '0';`
46			`else`
47			`case CURRENT_STATE is`
48			`when S0 =>`
49			`if start then`
50			`if (count = "000") then`
51			`NEXT_STATE <= S1;`
52			`en_shft <= '0';`
53			`en_count <= '1';`
54			`en_out <= '1';`
55			`sel1 <= '0';`
56			`sel2 <= '1';`
57			`c_count <= '0';`
58			`finish <= '0';`
59
60			`else`
61			`if (count = "001") then`
62			`NEXT_STATE <= S3;`
63			`en_shft <= '1';`
64			`en_count <= '1';`
65			`en_out <= '0';`
66			`sel1 <= '0';`
67			`sel2 <= '1';`
68			`c_count <= '0';`
69			`finish <= '0';`
70
71			`else`
72			`if (count = "111") then`
73			`NEXT_STATE <= S10;`
74			`en_shft <= '0';`
75			`en_count <= '0';`
76			`en_out <= '0';`
77			`sel1 <= '0';`
78			`sel2 <= '0';`
79			`c_count <= '0';`
80			`finish <= '1';`
81
82			`else`
83			`NEXT_STATE <= S6;`
84			`en_shft <= '0';`
85			`en_count <= '0';`
86			`en_out <= '0';`
87			`sel1 <= '0';`
88			`sel2 <= '0';`
89			`c_count <= '0';`
90			`finish <= '0';`
91
92			`end if;`
93			`end if;`
94			`end if;`
95
96			`else`
97			`NEXT_STATE <= S0;`
98			`en_shft <= '0';`
99			`en_count <= '0';`
100			`en_out <= '0';`
101			`sel1 <= '0';`
102			`sel2 <= '0';`
103			`c_count <= '0';`
104			`finish <= '0';`
105
106			`end if;`
107
108			`when S1 =>`
109			`NEXT_STATE <= S2;`
110			`en_shft <= '0';`
111			`en_count <= '1';`
112			`en_out <= '0';`
113			`sel1 <= '0';`
114			`sel2 <= '1';`
115			`c_count <= '1';`
116			`finish <= '0';`
117
118			`when S2 =>`
119			`NEXT_STATE <= S2;`
120			`en_shft <= '0';`
121			`en_count <= '1';`
122			`en_out <= '0';`
123			`sel1 <= '0';`
124			`sel2 <= '1';`
125			`c_count <= '1';`
126			`finish <= '0';`
127
128			`when S3 =>`
129			`NEXT_STATE <= S4;`
130			`en_shft <= '0';`
131			`en_count <= '1';`
132			`en_out <= '1';`
133			`sel1 <= '0';`
134			`sel2 <= '1';`
135			`c_count <= '0';`
136			`finish <= '0';`
137
138			`when S4 =>`
139			`NEXT_STATE <= S5;`
140			`en_shft <= '0';`
141			`en_count <= '1';`
142			`en_out <= '0';`
143			`sel1 <= '0';`
144			`sel2 <= '1';`
145			`c_count <= '1';`
146			`finish <= '0';`
147
148			`when S5 =>`
149			`NEXT_STATE <= S5;`
150			`en_shft <= '0';`
151			`en_count <= '1';`
152			`en_out <= '0';`
153			`sel1 <= '0';`
154			`sel2 <= '1';`
155			`c_count <= '1';`
156			`finish <= '0';`
157
158			`when S6 =>`
159			`NEXT_STATE <= S7;`
160			`en_shft <= '1';`
161			`en_count <= '1';`
162			`en_out <= '0';`
163			`sel1 <= '0';`
164			`sel2 <= '1';`
165			`c_count <= '0';`
166			`finish <= '0';`
167
168			`when S7 =>`
169			`NEXT_STATE <= S8;`
170			`en_shft <= '0';`
171			`en_count <= '1';`
172			`en_out <= '1';`
173			`sel1 <= '0';`
174			`sel2 <= '1';`
175			`c_count <= '0';`
176			`finish <= '0';`
177
178			`when S8 =>`
179			`NEXT_STATE <= S9;`
180			`en_shft <= '0';`
181			`en_count <= '1';`
182			`en_out <= '0';`
183			`sel1 <= '0';`
184			`sel2 <= '1';`
185			`c_count <= '1';`
186			`finish <= '0';`
187
188			`when S9 =>`
189			`NEXT_STATE <= S9;`
190			`en_shft <= '0';`
191			`en_count <= '1';`
192			`en_out <= '0';`
193			`sel1 <= '0';`
194			`sel2 <= '1';`
195			`c_count <= '1';`
196			`finish <= '0';`
197
198			`when S10 =>`
199			`NEXT_STATE <= S10;`
200			`en_shft <= '0';`
201			`en_count <= '0';`
202			`en_out <= '0';`
203			`sel1 <= '0';`
204			`sel2 <= '0';`
205			`c_count <= '0';`
206			`finish <= '1';`
207
208			`end case;`
209			`end if;`
210			`end process;`
211
212			`process (clk)`
213			`begin`
214			`if ((clk = '0') and not(clk'STABLE)) then`
215			`CURRENT_STATE <= NEXT_STATE;`
216			`end if;`
217			`end process;`
218
219			`end STATE_MACHINE;`
220
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