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[/] [idea/] [trunk/] [fsm/] [key_regulator/] [kontrol_kuncix.fsm] - Blame information for rev 9

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1 6 marta 
--Nama file : kontrol_kuncix.fsm
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--Deskripsi : kontrol pembangkitan (pengaturan) kunci
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--Author    : Mas Adit
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--Tanggal  : 24 Agustus 2001
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entity kontrol_kuncix is
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port (
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        clk : in bit;
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        start : in bit;
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        rst : in bit;
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        f_enkey : in bit;
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        f_invmul : in bit;
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        f_invadd : in bit;
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        rst_all : out bit;
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        key_ready : out bit;
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        s_enkey : out bit;
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        s_invmul : out bit;
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        s_invadd : out bit;
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        vdd : in bit;
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        vss : in bit
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);
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end kontrol_kuncix;
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architecture STATE_MACHINE of kontrol_kuncix is
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type STATE_TYPE is (S0, S2, S3, S4, S5, S6, S7, S8, S9);
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        --pragma CLOCK clk
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        --pragma CURRENT_STATE CURRENT_STATE
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        --pragma NEXT_STATE NEXT_STATE
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signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
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begin
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process (CURRENT_STATE, rst, start, f_enkey, f_invmul, f_invadd)
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begin
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        if (rst = '1') then
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                NEXT_STATE <= S0;
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                rst_all <= '1';
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                s_enkey <= '0';
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                s_invmul <='0';
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                key_ready <= '0';
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                s_invadd <= '0';
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        else
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        case CURRENT_STATE is
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        when S0 =>
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                if (start = '1') then
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                        if (f_enkey = '0') then
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                                NEXT_STATE <= S3;
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                                rst_all <= '0';
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                                s_enkey <= '1';
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                                s_invmul <='0';
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                                key_ready <= '0';
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                                s_invadd <= '0';
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                        else
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                                NEXT_STATE <= S2;
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                                rst_all <= '0';
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                                s_enkey <= '0';
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                                s_invmul <='0';
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                                key_ready <= '0';
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                                s_invadd <= '0';
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                        end if;
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                else
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                        NEXT_STATE <= S0;
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                        rst_all <= '1';
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                        s_enkey <= '0';
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                        s_invmul <='0';
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                        key_ready <= '0';
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                        s_invadd <= '0';
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                end if;
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                when S3 =>
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                        NEXT_STATE <= S0;
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                        rst_all <= '1';
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                        s_enkey <= '0';
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                        s_invmul <='0';
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                        key_ready <= '0';
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                        s_invadd <= '0';
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                when S2 =>
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                        if (f_invmul = '0') then
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                                NEXT_STATE <= S4;
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                                rst_all <= '0';
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                                s_enkey <= '0';
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                                s_invmul <='1';
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                                key_ready <= '0';
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                                s_invadd <= '0';
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                        else
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                                NEXT_STATE <= S5;
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                                rst_all <= '0';
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                                s_enkey <= '0';
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                                s_invmul <='0';
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                                key_ready <= '0';
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                                s_invadd <= '0';
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                        end if;
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                        when S4 =>
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                        if (f_invadd = '0') then
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                                NEXT_STATE <= S6;
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                                rst_all <= '0';
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                                s_enkey <= '0';
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                                s_invmul <='1';
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                                key_ready <= '0';
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                                s_invadd <= '1';
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                        else
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                                NEXT_STATE <= S7;
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                                rst_all <= '0';
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                                s_enkey <= '0';
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                                s_invmul <='1';
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                                key_ready <= '0';
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                                s_invadd <= '0';
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                        end if;
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                        when S5 =>
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                        if (f_invadd = '0') then
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                                NEXT_STATE <= S8;
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                                rst_all <= '0';
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                                s_enkey <= '0';
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                                s_invmul <='0';
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                                key_ready <= '0';
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                                s_invadd <= '1';
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                        else
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                                NEXT_STATE <= S9;
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                                rst_all <= '0';
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                                s_enkey <= '0';
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                                s_invmul <='0';
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                                key_ready <= '1';
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                                s_invadd <= '0';
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                        end if;
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                        when S6 =>
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                        NEXT_STATE <= S6;
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                        rst_all <= '0';
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                        s_enkey <= '0';
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                        s_invmul <='1';
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                        key_ready <= '0';
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                        s_invadd <= '1';
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                        when S7 =>
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                        NEXT_STATE <= S7;
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                        rst_all <= '0';
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                        s_enkey <= '0';
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                        s_invmul <='1';
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                        key_ready <= '0';
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                        s_invadd <= '0';
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                        when S8 =>
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                        NEXT_STATE <= S8;
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                        rst_all <= '0';
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                        s_enkey <= '0';
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                        s_invmul <='0';
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                        key_ready <= '0';
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                        s_invadd <= '1';
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                        when S9 =>
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                        NEXT_STATE <= S9;
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                        rst_all <= '0';
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                        s_enkey <= '0';
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                        s_invmul <='0';
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                        key_ready <= '1';
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                        s_invadd <= '0';
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        end case;
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        end if;
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end process;
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process (clk)
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begin
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        if ((clk = '0') and not(clk'STABLE)) then
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                CURRENT_STATE <= NEXT_STATE;
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        end if;
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end process;
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end STATE_MACHINE;
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