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[/] [idea/] [trunk/] [fsm/] [key_regulator/] [kontrol_utama_invaddx.fsm] - Blame information for rev 9

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1 6 marta 
--Nama file : kontrol_utama_invaddx.fsm
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--Deskripsi : kontrol utama modul inv_add modulo (2^16 + 1)
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--Author    : Mas Adit
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--Tanggal  : 28 Agustus 2001
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entity kontrol_utama_invaddx is
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port (
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        clk : in bit;
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        rst : in bit;
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        start : in bit;
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        n_dtin : in bit_vector(4 downto 0);
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        n_dtout : in bit_vector(4 downto 0);
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        c_cdtin : out bit;
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        en_cdtin : out bit;
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        c_cdtout : out bit;
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        en_cdtout : out bit;
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        en_out : out bit;
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        en_in : out bit;
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        finish : out bit;
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        vdd : in bit;
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        vss : in bit
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);
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end kontrol_utama_invaddx;
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architecture fsm of kontrol_utama_invaddx is
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type STATE_TYPE is (S0, S1, S2, S3, S4);
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        --pragma CLOCK clk
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        --pragma CURRENT_STATE CURRENT_STATE
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        --pragma NEXT_STATE NEXT_STATE
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signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
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begin
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process (CURRENT_STATE, rst, start, n_dtout, n_dtin)
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begin
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        if (rst = '1') then
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                NEXT_STATE <= S0;
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                en_cdtin <= '0';
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                c_cdtin <= '0';
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                en_cdtout <= '0';
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                c_cdtout <= '0';
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                en_in <= '0';
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                en_out <= '0';
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                finish <= '0';
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        else
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                case CURRENT_STATE is
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                when S0 =>
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                if  (start = '1') then
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                        if not(n_dtout = "10010") then
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                                if (n_dtin = "00000") then
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                                        NEXT_STATE <= S1;
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                                        en_cdtin <= '1';
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                                        c_cdtin <= '0';
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                                        en_cdtout <= '1';
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                                        c_cdtout <= '0';
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                                        en_in <= '1';
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                                        en_out <= '0';
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                                        finish <= '0';
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                                else
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                                        NEXT_STATE <= S2;
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                                        en_cdtin <= '0';
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                                        c_cdtin <= '0';
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                                        en_cdtout <= '0';
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                                        c_cdtout <= '1';
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                                        en_in <= '1';
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                                        en_out <= '0';
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                                        finish <= '0';
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                                end if;
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                        else
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                                NEXT_STATE <= S4;
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                                en_cdtin <= '0';
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                                c_cdtin <= '0';
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                                en_cdtout <= '0';
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                                c_cdtout <= '0';
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                                en_in <= '0';
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                                en_out <= '0';
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                                finish <= '1';
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                        end if;
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                else
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                        NEXT_STATE <= S0;
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                        en_cdtin <= '0';
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                        c_cdtin <= '0';
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                        en_cdtout <= '0';
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                        c_cdtout <= '0';
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                        en_in <= '0';
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                        en_out <= '0';
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                        finish <= '0';
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                end if;
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                when S1 =>
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                        NEXT_STATE <= S3;
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                        en_cdtin <= '1';
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                        c_cdtin <= '1';
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                        en_cdtout <= '1';
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                        c_cdtout <= '0';
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                        en_in <= '0';
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                        en_out <= '1';
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                        finish <= '0';
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                when S2 =>
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                        NEXT_STATE <= S3;
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                        en_cdtin <= '1';
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                        c_cdtin <= '1';
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                        en_cdtout <= '1';
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                        c_cdtout <= '0';
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                        en_in <= '0';
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                        en_out <= '1';
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                        finish <= '0';
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                when S3 =>
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                        NEXT_STATE <= S3;
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                        en_cdtin <= '1';
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                        c_cdtin <= '1';
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                        en_cdtout <= '1';
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                        c_cdtout <= '0';
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                        en_in <= '0';
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                        en_out <= '1';
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                        finish <= '0';
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                when S4 =>
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                        NEXT_STATE <= S4;
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                        en_cdtin <= '0';
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                        c_cdtin <= '0';
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                        en_cdtout <= '0';
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                        c_cdtout <= '0';
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                        en_in <= '0';
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                        en_out <= '0';
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                        finish <= '1';
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                end case;
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        end if;
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end process;
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process (clk)
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begin
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        if ((clk = '0') and not(clk'STABLE)) then
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                CURRENT_STATE <= NEXT_STATE;
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        end if;
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end process;
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end fsm;
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