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-- File Name    : ofb.fsm
2 
-- Version      : v1.2
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-- Description  : finite state mechine description of ofb mode
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-- Purpose      : to generate behavioral description of ofb mode
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-- Author       : Sigit Dewantoro
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-- Address      : IS Laboratory, Labtek VIII, ITB, Jl. Ganesha 10, Bandung, Indonesia
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-- Email        : sigit@students.ee.itb.ac.id, sigit@ic.vlsi.itb.ac.id
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-- Date         : August 23th, 2001
9 
 
10 
entity ofb is
11 
PORT (
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        active          : in BIT;
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        clk             : in BIT;
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        key_ready       : in BIT;
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        dt_ready        : in BIT;
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        finish          : in BIT;
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        first_dt        : inout BIT;
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        E_mesin         : out BIT;
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        s_mesin         : out BIT;
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        emp_buf         : out BIT;
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        cp_ready        : out BIT;
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        cke_b_mode      : out BIT;
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        en_in           : out BIT;
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        en_iv           : out BIT;
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        en_rcbc         : out BIT;
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        en_out          : out BIT;
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        sel1            : out BIT_VECTOR (1 downto 0);
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        sel2            : out BIT_VECTOR (1 downto 0);
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        sel3            : out BIT_VECTOR (1 downto 0);
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        vdd             : in BIT;
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        vss             : in BIT
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     );
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end ofb;
34 
 
35 
architecture STATE_MACHINE of ofb is
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        type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13);
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        -- pragma CLOCK clk
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        -- pragma CURRENT_STATE CURRENT_STATE
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        -- pragma NEXT_STATE NEXT_STATE
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        signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
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44 
        begin
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        process (CURRENT_STATE, active, key_ready, dt_ready, first_dt, finish)
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                begin
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                if active then
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                        NEXT_STATE <= S0;
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                        E_mesin <= '1';
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                        s_mesin <= '0';
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                        emp_buf <= '0';
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                        cp_ready <= '0';
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                        cke_b_mode <= '0';
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                        en_in <= '0';
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                        en_iv <= '0';
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                        en_rcbc <= '0';
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                        en_out <= '0';
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                        first_dt <= '1';
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                        sel1 <= "10";
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                        sel2 <= "10";
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                        sel3 <= "10";
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                else
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                        case CURRENT_STATE is
64 
 
65 
                -- ***********************************************************************
66 
 
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                        when S0 =>
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                        NEXT_STATE <= S1;
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                        E_mesin <= '1';
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                        s_mesin <= '0';
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                        emp_buf <= '0';
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                        cp_ready <= '0';
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                        cke_b_mode <= '1';
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                        en_in <= '0';
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                        en_iv <= '0';
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                        en_rcbc <= '0';
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                        en_out <= '0';
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                        first_dt <= '1';
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                        sel1 <= "10";
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                        sel2 <= "10";
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                        sel3 <= "10";
82 
 
83 
                -- ***********************************************************************
84 
 
85 
                        when S1 =>
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                        if (key_ready and dt_ready) then
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                                if first_dt then
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                                        NEXT_STATE <= S2;
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                                        E_mesin <= '1';
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                                        s_mesin <= '0';
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                                        emp_buf <= '1';
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                                        cp_ready <= '0';
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                                        cke_b_mode <= '1';
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                                        en_in <= '1';
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                                        en_iv <= '0';
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                                        en_rcbc <= '0';
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                                        en_out <= '0';
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                                        first_dt <= '1';
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                                        sel1 <= "01";
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                                        sel2 <= "10";
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                                        sel3 <= "10";
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                                else
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                                        NEXT_STATE <= S5;
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                                        E_mesin <= '1';
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                                        s_mesin <= '0';
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                                        emp_buf <= '0';
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                                        cp_ready <= '0';
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                                        cke_b_mode <= '1';
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                                        en_in <= '0';
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                                        en_iv <= '0';
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                                        en_rcbc <= '0';
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                                        en_out <= '0';
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                                        first_dt <= '1';
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                                        sel1 <= "10";
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                                        sel2 <= "01";
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                                        sel3 <= "01";
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                                end if;
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                        else
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                                NEXT_STATE <= S1;
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                                E_mesin <= '1';
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                                s_mesin <= '0';
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                                emp_buf <= '0';
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                                cp_ready <= '0';
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                                cke_b_mode <= '1';
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                                en_in <= '0';
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                                en_iv <= '0';
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                                en_rcbc <= '0';
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                                en_out <= '0';
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                                first_dt <= '1';
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                                sel1 <= "10";
131 
                                sel2 <= "10";
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                                sel3 <= "10";
133 
                        end if;
134 
 
135 
                -- ***********************************************************************
136 
 
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                        when S2 =>
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                        NEXT_STATE <= S3;
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                        E_mesin <= '1';
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                        s_mesin <= '0';
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                        emp_buf <= '0';
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                        cp_ready <= '0';
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                        cke_b_mode <= '1';
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                        en_in <= '0';
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                        en_iv <= '1';
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                        en_rcbc <= '0';
147 
                        en_out <= '0';
148 
                        first_dt <= '0';
149 
                        sel1 <= "01";
150 
                        sel2 <= "10";
151 
                        sel3 <= "10";
152 
 
153 
                -- ***********************************************************************
154 
 
155 
                        when S3 =>
156 
                        NEXT_STATE <= S4;
157 
                        E_mesin <= '1';
158 
                        s_mesin <= '0';
159 
                        emp_buf <= '0';
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                        cp_ready <= '0';
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                        cke_b_mode <= '1';
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                        en_in <= '0';
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                        en_iv <= '0';
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                        en_rcbc <= '0';
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                        en_out <= '0';
166 
                        first_dt <= '0';
167 
                        sel1 <= "10";
168 
                        sel2 <= "01";
169 
                        sel3 <= "10";
170 
 
171 
                -- ***********************************************************************
172 
 
173 
                        when S4 =>
174 
                        NEXT_STATE <= S6;
175 
                        E_mesin <= '1';
176 
                        s_mesin <= '1';
177 
                        emp_buf <= '0';
178 
                        cp_ready <= '0';
179 
                        cke_b_mode <= '1';
180 
                        en_in <= '0';
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                        en_iv <= '0';
182 
                        en_rcbc <= '0';
183 
                        en_out <= '0';
184 
                        first_dt <= '0';
185 
                        sel1 <= "10";
186 
                        sel2 <= "10";
187 
                        sel3 <= "10";
188 
 
189 
                -- ***********************************************************************
190 
 
191 
                        when S5 =>
192 
                        NEXT_STATE <= S6;
193 
                        E_mesin <= '1';
194 
                        s_mesin <= '1';
195 
                        emp_buf <= '0';
196 
                        cp_ready <= '0';
197 
                        cke_b_mode <= '1';
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                        en_in <= '0';
199 
                        en_iv <= '0';
200 
                        en_rcbc <= '0';
201 
                        en_out <= '0';
202 
                        first_dt <= '0';
203 
                        sel1 <= "10";
204 
                        sel2 <= "10";
205 
                        sel3 <= "10";
206 
 
207 
                -- ***********************************************************************
208 
 
209 
                        when S6 =>
210 
                        NEXT_STATE <= S7;
211 
                        E_mesin <= '1';
212 
                        s_mesin <= '1';
213 
                        emp_buf <= '0';
214 
                        cp_ready <= '0';
215 
                        cke_b_mode <= '1';
216 
                        en_in <= '0';
217 
                        en_iv <= '0';
218 
                        en_rcbc <= '0';
219 
                        en_out <= '0';
220 
                        first_dt <= '0';
221 
                        sel1 <= "10";
222 
                        sel2 <= "10";
223 
                        sel3 <= "10";
224 
 
225 
                -- ***********************************************************************
226 
 
227 
                        when S7 =>
228 
                        if (finish and dt_ready) then
229 
                                NEXT_STATE <= S8;
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                                E_mesin <= '1';
231 
                                s_mesin <= '0';
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                                emp_buf <= '1';
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                                cp_ready <= '0';
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                                cke_b_mode <= '1';
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                                en_in <= '1';
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                                en_iv <= '0';
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                                en_rcbc <= '0';
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                                en_out <= '0';
239 
                                first_dt <= '0';
240 
                                sel1 <= "00";
241 
                                sel2 <= "10";
242 
                                sel3 <= "10";
243 
                        else
244 
                                NEXT_STATE <= S7;
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                                E_mesin <= '1';
246 
                                s_mesin <= '1';
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                                emp_buf <= '0';
248 
                                cp_ready <= '0';
249 
                                cke_b_mode <= '1';
250 
                                en_in <= '0';
251 
                                en_iv <= '0';
252 
                                en_rcbc <= '0';
253 
                                en_out <= '0';
254 
                                first_dt <= '0';
255 
                                sel1 <= "10";
256 
                                sel2 <= "10";
257 
                                sel3 <= "10";
258 
                        end if;
259 
 
260 
                -- ***********************************************************************
261 
 
262 
                        when S8 =>
263 
                        NEXT_STATE <= S9;
264 
                        E_mesin <= '1';
265 
                        s_mesin <= '0';
266 
                        emp_buf <= '1';
267 
                        cp_ready <= '0';
268 
                        cke_b_mode <= '1';
269 
                        en_in <= '1';
270 
                        en_iv <= '1';
271 
                        en_rcbc <= '0';
272 
                        en_out <= '0';
273 
                        first_dt <= '0';
274 
                        sel1 <= "00";
275 
                        sel2 <= "10";
276 
                        sel3 <= "10";
277 
 
278 
                -- ***********************************************************************
279 
 
280 
                        when S9 =>
281 
                        NEXT_STATE <= S10;
282 
                        E_mesin <= '1';
283 
                        s_mesin <= '0';
284 
                        emp_buf <= '0';
285 
                        cp_ready <= '0';
286 
                        cke_b_mode <= '1';
287 
                        en_in <= '0';
288 
                        en_iv <= '0';
289 
                        en_rcbc <= '0';
290 
                        en_out <= '0';
291 
                        first_dt <= '0';
292 
                        sel1 <= "10";
293 
                        sel2 <= "10";
294 
                        sel3 <= "01";
295 
 
296 
                -- ***********************************************************************
297 
 
298 
                        when S10 =>
299 
                        NEXT_STATE <= S11;
300 
                        E_mesin <= '1';
301 
                        s_mesin <= '0';
302 
                        emp_buf <= '0';
303 
                        cp_ready <= '0';
304 
                        cke_b_mode <= '1';
305 
                        en_in <= '0';
306 
                        en_iv <= '0';
307 
                        en_rcbc <= '0';
308 
                        en_out <= '1';
309 
                        first_dt <= '0';
310 
                        sel1 <= "10";
311 
                        sel2 <= "10";
312 
                        sel3 <= "01";
313 
 
314 
                -- ***********************************************************************
315 
 
316 
                        when S11 =>
317 
                        NEXT_STATE <= S12;
318 
                        E_mesin <= '1';
319 
                        s_mesin <= '0';
320 
                        emp_buf <= '0';
321 
                        cp_ready <= '1';
322 
                        cke_b_mode <= '1';
323 
                        en_in <= '0';
324 
                        en_iv <= '0';
325 
                        en_rcbc <= '0';
326 
                        en_out <= '0';
327 
                        first_dt <= '0';
328 
                        sel1 <= "10";
329 
                        sel2 <= "10";
330 
                        sel3 <= "01";
331 
 
332 
                -- ***********************************************************************
333 
 
334 
                        when S12 =>
335 
                        NEXT_STATE <= S13;
336 
                        E_mesin <= '1';
337 
                        s_mesin <= '0';
338 
                        emp_buf <= '0';
339 
                        cp_ready <= '0';
340 
                        cke_b_mode <= '1';
341 
                        en_in <= '0';
342 
                        en_iv <= '0';
343 
                        en_rcbc <= '0';
344 
                        en_out <= '0';
345 
                        first_dt <= '0';
346 
                        sel1 <= "10";
347 
                        sel2 <= "10";
348 
                        sel3 <= "01";
349 
 
350 
                -- ***********************************************************************
351 
 
352 
                        when S13 =>
353 
                        NEXT_STATE <= S13;
354 
                        E_mesin <= '1';
355 
                        s_mesin <= '0';
356 
                        emp_buf <= '0';
357 
                        cp_ready <= '0';
358 
                        cke_b_mode <= '1';
359 
                        en_in <= '0';
360 
                        en_iv <= '0';
361 
                        en_rcbc <= '0';
362 
                        en_out <= '0';
363 
                        first_dt <= '0';
364 
                        sel1 <= "10";
365 
                        sel2 <= "10";
366 
                        sel3 <= "01";
367 
 
368 
                -- ***********************************************************************
369 
 
370 
                        end case;
371 
                end if;
372 
        end process;
373 
 
374 
        process(clk)
375 
                begin
376 
                if(clk = '0' and not clk' stable) then
377 
                        CURRENT_STATE <= NEXT_STATE;
378 
                end if;
379 
       end process;
380 
 
381 
end STATE_MACHINE;

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