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marta |
-- File Name : mul17.pat --
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-- Description : The test patterns of the 17-bit multiplier --
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-- for the normal verification of the structural view --
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-- with zero delay --
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-- Purpose : To be used by ASIMUT --
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-- Date : Aug 23, 2001 --
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-- Version : 1.1 --
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-- Author : Martadinata A. --
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-- Address : VLSI RG, Dept. of Electrical Engineering ITB --
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-- Bandung, Indonesia --
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-- E-mail : marta@ic.vlsi.itb.ac.id --
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in vdd;;
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in vss;;
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in a(16 downto 0);;
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in b(16 downto 0);;
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out sum(31 downto 0) X;;
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begin
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path_1 : 1 0 00000000000000000 00000000000000000 ?00000000;
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path_2 : 1 0 00000000000000001 00000000000000000 ?00000000;
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path_3 : 1 0 00000000000000001 00000000000000001 ?00000001;
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path_4 : 1 0 00000000000000111 00000000000000010 ?0000000E;
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path_5 : 1 0 00000000000001000 00000000000000100 ?00000020;
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path_6 : 1 0 00000000011111111 00000000000000001 ?000000FF;
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path_7 : 1 0 00111111111111111 00000000000000001 ?00007FFF;
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path_8 : 1 0 00111111111111111 00000000000000010 ?0000FFFE;
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path_9 : 1 0 11111111111111111 00000000000000001 ?0001FFFF;
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path_10 : 1 0 11111111111111111 00000000011111111 ?01FDFF01;
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path_11 : 1 0 10000000000000000 01111111111111111 ?FFFF0000;
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path_12 : 1 0 10000000000000000 01000100010001000 ?88880000;
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end;
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