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marta |
-- File Name : sm16adder.pat --
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-- Description : The test patterns of the synchronized modulo 2^16 adder --
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-- for the normal verification of the structural view --
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-- with zero delay --
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-- Purpose : To be used by ASIMUT --
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-- Date : Aug 22, 2001 --
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-- Version : 1.1 --
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-- Author : Martadinata A. --
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-- Address : VLSI RG, Dept. of Electrical Engineering ITB --
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-- Bandung, Indonesia --
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-- E-mail : marta@ic.vlsi.itb.ac.id --
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in vdd;;
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in vss;;
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in a(15 downto 0) X;;
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in b(15 downto 0) X;;
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in en ;;
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in clr ;;
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out s(15 downto 0) X;;
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begin
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path_1 : 1 0 0000 0000 1 0 ?0000;
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path_2 : 1 0 0000 0000 0 0 ?0000;
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path_3 : 1 0 0000 00AB 1 0 ?00AB;
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path_4 : 1 0 0000 00AB 0 0 ?00AB;
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path_5 : 1 0 0000 CDAB 1 0 ?CDAB;
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path_6 : 1 0 0000 CDAB 0 0 ?CDAB;
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path_7 : 1 0 00AB 0000 1 0 ?00AB;
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path_8 : 1 0 00AB 0000 0 0 ?00AB;
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path_9 : 1 0 CDAB 0000 1 0 ?CDAB;
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path_10 : 1 0 CDAB 0000 0 0 ?CDAB;
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path_11 : 1 0 CDAB 8888 1 0 ?5633;
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path_12 : 1 0 CDAB 8888 0 0 ?5633;
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path_13 : 1 0 8888 FFFF 1 0 ?8887;
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path_14 : 1 0 8888 FFFF 0 0 ?8887;
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path_15 : 1 0 EEEE CCCC 1 0 ?BBBA;
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path_16 : 1 0 EEEE CCCC 0 0 ?BBBA;
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end;
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