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[/] [idea/] [trunk/] [structural_c/] [idea_machine/] [sm16plus1mul.c] - Blame information for rev 9

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1 7 marta
/* File Name   : sm16plus1mul.c                                         */
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/* Description : The synchronized modulo 2^16+1 multiplier              */
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/* Purpose     : To be used by GENLIB                                   */
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/* Date        : Aug 23, 2001                                           */
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/* Version     : 1.1                                                    */
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/* Author      : Martadinata A.                                         */
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/* Address     : VLSI RG, Dept. of Electrical Engineering ITB,          */
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/*               Bandung, Indonesia                                     */
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/* E-mail      : marta@ic.vlsi.itb.ac.id                                */
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#include<genlib.h>
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main()
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{
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 DEF_LOFIG("sm16plus1mul");
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 LOCON("in1[0:15]",     IN,  "in1[0:15]"    );
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 LOCON("in2[0:15]",     IN,  "in2[0:15]"    );
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 LOCON("en",            IN,  "en"           );
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 LOCON("clr",           IN,  "clr"          );
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 LOCON("mulout[0:15]", OUT,  "mulout[0:15]" );
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 LOCON("vdd",           IN,  "vdd"          );
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 LOCON("vss",           IN,  "vss"          );
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 LOINS("comp1_glopg","com1a","in1[15:0]","kout1a[16:0]","vdd","vss",0);
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 LOINS("comp1_glopg","com1b","in2[15:0]","kout1b[16:0]","vdd","vss",0);
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 LOINS("mul17_glopg","mul","kout1a[16:0]","kout1b[16:0]","res[31:0]","vdd","vss",0);
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 LOINS("comp2_glopg","com2","vss","vdd","kout2[0:15]","res[16:31]","res[0:15]",0);
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 LOINS("subtract16_glopg","sub","res[0:15]","res[16:31]","dif[0:15]","vdd","vss",0);
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 LOINS("reg16_glopf","reg1","kout2[0:15]","en","clr","r1[0:15]","vdd","vss",0);
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 LOINS("reg16_glopf","reg2","dif[0:15]","en","clr","r2[0:15]","vdd","vss",0);
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 LOINS("m16adder_glopg","add","r2[0:15]","r1[0:15]","mulout[0:15]","vdd","vss",0);
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 SAVE_LOFIG();
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 exit(0);
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}

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