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/*! \file enc28j60.c \brief Microchip ENC28J60 Ethernet Interface Driver. */
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//*****************************************************************************
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//
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// File Name : 'enc28j60.c'
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// Title : Microchip ENC28J60 Ethernet Interface Driver
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// Author : Pascal Stang (c)2005
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// Created : 9/22/2005
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// Revised : 9/22/2005
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// Version : 0.1
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// Target MCU : Atmel AVR series
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// Editor Tabs : 4
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//
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// Description : This driver provides initialization and transmit/receive
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// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.
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// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin
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// chip, using an SPI interface to the host processor.
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//
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//*****************************************************************************
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#include "avr/io.h"
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#include "global.h"
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#include "timer.h"
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#include "rprintf.h"
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#include "enc28j60.h"
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/*
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#ifdef SPDR0
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#define SPDR SPDR0
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#define SPCR SPCR0
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#define SPSR SPSR0
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#define SPIF SPIF0
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#define MSTR MSTR0
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#define CPOL CPOL0
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#define DORD DORD0
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#define SPR0 SPR00
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#define SPR1 SPR01
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#define SPI2X SPI2X0
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#define SPE SPE0
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#endif
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*/
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// include configuration
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#include "enc28j60conf.h"
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u08 Enc28j60Bank;
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u16 NextPacketPtr;
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void nicInit(void)
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{
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enc28j60Init();
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}
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void nicSend(unsigned int len, unsigned char* packet)
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{
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enc28j60PacketSend(len, packet);
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}
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unsigned int nicPoll(unsigned int maxlen, unsigned char* packet)
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{
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return enc28j60PacketReceive(maxlen, packet);
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}
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void nicGetMacAddress(u08* macaddr)
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{
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// read MAC address registers
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// NOTE: MAC address in ENC28J60 is byte-backward
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*macaddr++ = enc28j60Read(MAADR5);
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*macaddr++ = enc28j60Read(MAADR4);
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*macaddr++ = enc28j60Read(MAADR3);
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*macaddr++ = enc28j60Read(MAADR2);
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*macaddr++ = enc28j60Read(MAADR1);
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*macaddr++ = enc28j60Read(MAADR0);
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}
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void nicSetMacAddress(u08* macaddr)
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{
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// write MAC address
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// NOTE: MAC address in ENC28J60 is byte-backward
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enc28j60Write(MAADR5, *macaddr++);
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enc28j60Write(MAADR4, *macaddr++);
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enc28j60Write(MAADR3, *macaddr++);
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enc28j60Write(MAADR2, *macaddr++);
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enc28j60Write(MAADR1, *macaddr++);
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enc28j60Write(MAADR0, *macaddr++);
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}
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void nicRegDump(void)
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{
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enc28j60RegDump();
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}
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/*
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void ax88796SetupPorts(void)
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{
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#if NIC_CONNECTION == MEMORY_MAPPED
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// enable external SRAM interface - no wait states
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sbi(MCUCR, SRE);
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// sbi(MCUCR, SRW10);
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// sbi(XMCRA, SRW00);
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// sbi(XMCRA, SRW01);
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// sbi(XMCRA, SRW11);
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#else
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// set address port to output
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AX88796_ADDRESS_DDR = AX88796_ADDRESS_MASK;
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// set data port to input with pull-ups
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AX88796_DATA_DDR = 0x00;
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AX88796_DATA_PORT = 0xFF;
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// initialize the control port read and write pins to de-asserted
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sbi( AX88796_CONTROL_PORT, AX88796_CONTROL_READPIN );
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sbi( AX88796_CONTROL_PORT, AX88796_CONTROL_WRITEPIN );
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// set the read and write pins to output
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sbi( AX88796_CONTROL_DDR, AX88796_CONTROL_READPIN );
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sbi( AX88796_CONTROL_DDR, AX88796_CONTROL_WRITEPIN );
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#endif
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// set reset pin to output
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sbi( AX88796_RESET_DDR, AX88796_RESET_PIN );
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}
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*/
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u08 enc28j60ReadOp(u08 op, u08 address)
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{
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u08 data;
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// assert CS
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ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);
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// issue read command
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SPDR = op | (address & ADDR_MASK);
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while(!(SPSR & (1<<SPIF)));
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// read data
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SPDR = 0x00;
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while(!(SPSR & (1<<SPIF)));
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// do dummy read if needed
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if(address & 0x80)
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{
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SPDR = 0x00;
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while(!(inb(SPSR) & (1<<SPIF)));
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}
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data = SPDR;
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// release CS
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ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
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return data;
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}
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void enc28j60WriteOp(u08 op, u08 address, u08 data)
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{
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// assert CS
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ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);
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// issue write command
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SPDR = op | (address & ADDR_MASK);
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while(!(SPSR & (1<<SPIF)));
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// write data
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SPDR = data;
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while(!(SPSR & (1<<SPIF)));
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// release CS
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ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
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}
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void enc28j60ReadBuffer(u16 len, u08* data)
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{
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// assert CS
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ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);
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// issue read command
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SPDR = ENC28J60_READ_BUF_MEM;
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while(!(SPSR & (1<<SPIF)));
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while(len--)
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{
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// read data
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SPDR = 0x00;
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while(!(SPSR & (1<<SPIF)));
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*data++ = SPDR;
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}
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// release CS
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ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
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}
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void enc28j60WriteBuffer(u16 len, u08* data)
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{
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// assert CS
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ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);
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// issue write command
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SPDR = ENC28J60_WRITE_BUF_MEM;
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while(!(SPSR & (1<<SPIF)));
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while(len--)
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{
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// write data
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SPDR = *data++;
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while(!(SPSR & (1<<SPIF)));
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}
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// release CS
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ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
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}
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void enc28j60SetBank(u08 address)
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{
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// set the bank (if needed)
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if((address & BANK_MASK) != Enc28j60Bank)
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{
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// set the bank
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enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
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enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);
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Enc28j60Bank = (address & BANK_MASK);
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}
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}
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u08 enc28j60Read(u08 address)
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{
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// set the bank
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enc28j60SetBank(address);
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// do the read
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return enc28j60ReadOp(ENC28J60_READ_CTRL_REG, address);
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}
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void enc28j60Write(u08 address, u08 data)
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{
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// set the bank
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enc28j60SetBank(address);
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// do the write
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enc28j60WriteOp(ENC28J60_WRITE_CTRL_REG, address, data);
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}
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u16 enc28j60PhyRead(u08 address)
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{
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u16 data;
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// Set the right address and start the register read operation
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enc28j60Write(MIREGADR, address);
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enc28j60Write(MICMD, MICMD_MIIRD);
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// wait until the PHY read completes
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while(enc28j60Read(MISTAT) & MISTAT_BUSY);
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// quit reading
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enc28j60Write(MICMD, 0x00);
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// get data value
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data = enc28j60Read(MIRDL);
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data |= enc28j60Read(MIRDH);
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// return the data
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return data;
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}
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void enc28j60PhyWrite(u08 address, u16 data)
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{
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// set the PHY register address
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enc28j60Write(MIREGADR, address);
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// write the PHY data
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enc28j60Write(MIWRL, data);
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enc28j60Write(MIWRH, data>>8);
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// wait until the PHY write completes
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while(enc28j60Read(MISTAT) & MISTAT_BUSY);
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}
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void enc28j60Init(void)
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{
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// initialize I/O
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sbi(ENC28J60_CONTROL_DDR, ENC28J60_CONTROL_CS);
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sbi(ENC28J60_CONTROL_PORT, ENC28J60_CONTROL_CS);
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// setup SPI I/O pins
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// SCK should be low!
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cbi(ENC28J60_SPI_PORT, ENC28J60_SPI_SCK); // set SCK hi
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sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SCK); // set SCK as output
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cbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MISO); // set MISO as input
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sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MOSI); // set MOSI as output
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sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SS); // SS must be output for Master mode to work
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// initialize SPI interface
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// master mode
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sbi(SPCR, MSTR);
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// select clock phase positive-going in middle of data
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cbi(SPCR, CPOL);
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// select clock phase
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cbi(SPCR, CPHA);
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// Data order MSB first
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cbi(SPCR,DORD);
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// switch to f/4 2X = f/2 bitrate
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cbi(SPCR, SPR0);
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sbi(SPCR, SPR1);
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// No dual datarate
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cbi(SPSR, SPI2X);
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// enable SPI
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sbi(SPCR, SPE);
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296 |
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// perform system reset
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enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
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// check CLKRDY bit to see if reset is complete
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delay_us(50);
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while(!(enc28j60Read(ESTAT) & ESTAT_CLKRDY));
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// do bank 0 stuff
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// initialize receive buffer
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// 16-bit transfers, must write low byte first
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// set receive buffer start address
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NextPacketPtr = RXSTART_INIT;
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enc28j60Write(ERXSTL, RXSTART_INIT&0xFF);
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enc28j60Write(ERXSTH, RXSTART_INIT>>8);
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// set receive pointer address
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enc28j60Write(ERXRDPTL, RXSTART_INIT&0xFF);
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enc28j60Write(ERXRDPTH, RXSTART_INIT>>8);
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// set receive buffer end
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// ERXND defaults to 0x1FFF (end of ram)
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enc28j60Write(ERXNDL, RXSTOP_INIT&0xFF);
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enc28j60Write(ERXNDH, RXSTOP_INIT>>8);
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// set transmit buffer start
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// ETXST defaults to 0x0000 (beginnging of ram)
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enc28j60Write(ETXSTL, TXSTART_INIT&0xFF);
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enc28j60Write(ETXSTH, TXSTART_INIT>>8);
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320 |
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321 |
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// do bank 2 stuff
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322 |
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// enable MAC receive
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323 |
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enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
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324 |
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// bring MAC out of reset
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enc28j60Write(MACON2, 0x00);
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// enable automatic padding and CRC operations
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enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
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// enc28j60Write(MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
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// set inter-frame gap (non-back-to-back)
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enc28j60Write(MAIPGL, 0x12);
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enc28j60Write(MAIPGH, 0x0C);
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// set inter-frame gap (back-to-back)
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enc28j60Write(MABBIPG, 0x12);
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// Set the maximum packet size which the controller will accept
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enc28j60Write(MAMXFLL, MAX_FRAMELEN&0xFF);
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enc28j60Write(MAMXFLH, MAX_FRAMELEN>>8);
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337 |
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// do bank 3 stuff
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339 |
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// write MAC address
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340 |
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// NOTE: MAC address in ENC28J60 is byte-backward
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341 |
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enc28j60Write(MAADR5, ENC28J60_MAC0);
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enc28j60Write(MAADR4, ENC28J60_MAC1);
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enc28j60Write(MAADR3, ENC28J60_MAC2);
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enc28j60Write(MAADR2, ENC28J60_MAC3);
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345 |
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enc28j60Write(MAADR1, ENC28J60_MAC4);
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346 |
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enc28j60Write(MAADR0, ENC28J60_MAC5);
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347 |
|
|
|
348 |
|
|
// no loopback of transmitted frames
|
349 |
|
|
enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS);
|
350 |
|
|
|
351 |
|
|
// switch to bank 0
|
352 |
|
|
enc28j60SetBank(ECON1);
|
353 |
|
|
// enable interrutps
|
354 |
|
|
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
|
355 |
|
|
// enable packet reception
|
356 |
|
|
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
|
357 |
|
|
/*
|
358 |
|
|
enc28j60PhyWrite(PHLCON, 0x0AA2);
|
359 |
|
|
|
360 |
|
|
// setup duplex ----------------------
|
361 |
|
|
|
362 |
|
|
// Disable receive logic and abort any packets currently being transmitted
|
363 |
|
|
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS|ECON1_RXEN);
|
364 |
|
|
|
365 |
|
|
{
|
366 |
|
|
u16 temp;
|
367 |
|
|
// Set the PHY to the proper duplex mode
|
368 |
|
|
temp = enc28j60PhyRead(PHCON1);
|
369 |
|
|
temp &= ~PHCON1_PDPXMD;
|
370 |
|
|
enc28j60PhyWrite(PHCON1, temp);
|
371 |
|
|
// Set the MAC to the proper duplex mode
|
372 |
|
|
temp = enc28j60Read(MACON3);
|
373 |
|
|
temp &= ~MACON3_FULDPX;
|
374 |
|
|
enc28j60Write(MACON3, temp);
|
375 |
|
|
}
|
376 |
|
|
|
377 |
|
|
// Set the back-to-back inter-packet gap time to IEEE specified
|
378 |
|
|
// requirements. The meaning of the MABBIPG value changes with the duplex
|
379 |
|
|
// state, so it must be updated in this function.
|
380 |
|
|
// In full duplex, 0x15 represents 9.6us; 0x12 is 9.6us in half duplex
|
381 |
|
|
//enc28j60Write(MABBIPG, DuplexState ? 0x15 : 0x12);
|
382 |
|
|
|
383 |
|
|
// Reenable receive logic
|
384 |
|
|
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
|
385 |
|
|
|
386 |
|
|
// setup duplex ----------------------
|
387 |
|
|
*/
|
388 |
|
|
}
|
389 |
|
|
|
390 |
|
|
void enc28j60PacketSend(unsigned int len, unsigned char* packet)
|
391 |
|
|
{
|
392 |
|
|
// Set the write pointer to start of transmit buffer area
|
393 |
|
|
enc28j60Write(EWRPTL, TXSTART_INIT);
|
394 |
|
|
enc28j60Write(EWRPTH, TXSTART_INIT>>8);
|
395 |
|
|
// Set the TXND pointer to correspond to the packet size given
|
396 |
|
|
enc28j60Write(ETXNDL, (TXSTART_INIT+len));
|
397 |
|
|
enc28j60Write(ETXNDH, (TXSTART_INIT+len)>>8);
|
398 |
|
|
|
399 |
|
|
// write per-packet control byte
|
400 |
|
|
enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
|
401 |
|
|
|
402 |
|
|
// copy the packet into the transmit buffer
|
403 |
|
|
enc28j60WriteBuffer(len, packet);
|
404 |
|
|
|
405 |
|
|
// send the contents of the transmit buffer onto the network
|
406 |
|
|
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
|
407 |
|
|
}
|
408 |
|
|
|
409 |
|
|
unsigned int enc28j60PacketReceive(unsigned int maxlen, unsigned char* packet)
|
410 |
|
|
{
|
411 |
|
|
u16 rxstat;
|
412 |
|
|
u16 len;
|
413 |
|
|
|
414 |
|
|
// check if a packet has been received and buffered
|
415 |
|
|
// if( !(enc28j60Read(EIR) & EIR_PKTIF) )
|
416 |
|
|
if( !enc28j60Read(EPKTCNT) )
|
417 |
|
|
return 0;
|
418 |
|
|
|
419 |
|
|
// Make absolutely certain that any previous packet was discarded
|
420 |
|
|
//if( WasDiscarded == FALSE)
|
421 |
|
|
// MACDiscardRx();
|
422 |
|
|
|
423 |
|
|
// Set the read pointer to the start of the received packet
|
424 |
|
|
enc28j60Write(ERDPTL, (NextPacketPtr));
|
425 |
|
|
enc28j60Write(ERDPTH, (NextPacketPtr)>>8);
|
426 |
|
|
// read the next packet pointer
|
427 |
|
|
NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
|
428 |
|
|
NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
|
429 |
|
|
// read the packet length
|
430 |
|
|
len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
|
431 |
|
|
len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
|
432 |
|
|
// read the receive status
|
433 |
|
|
rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
|
434 |
|
|
rxstat |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
|
435 |
|
|
|
436 |
|
|
// limit retrieve length
|
437 |
|
|
// (we reduce the MAC-reported length by 4 to remove the CRC)
|
438 |
|
|
len = MIN(len, maxlen);
|
439 |
|
|
|
440 |
|
|
// copy the packet from the receive buffer
|
441 |
|
|
enc28j60ReadBuffer(len, packet);
|
442 |
|
|
|
443 |
|
|
// Move the RX read pointer to the start of the next received packet
|
444 |
|
|
// This frees the memory we just read out
|
445 |
|
|
enc28j60Write(ERXRDPTL, (NextPacketPtr));
|
446 |
|
|
enc28j60Write(ERXRDPTH, (NextPacketPtr)>>8);
|
447 |
|
|
|
448 |
|
|
// decrement the packet counter indicate we are done with this packet
|
449 |
|
|
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
|
450 |
|
|
|
451 |
|
|
return len;
|
452 |
|
|
}
|
453 |
|
|
|
454 |
|
|
void enc28j60ReceiveOverflowRecover(void)
|
455 |
|
|
{
|
456 |
|
|
// receive buffer overflow handling procedure
|
457 |
|
|
|
458 |
|
|
// recovery completed
|
459 |
|
|
}
|
460 |
|
|
|
461 |
|
|
void enc28j60RegDump(void)
|
462 |
|
|
{
|
463 |
|
|
// unsigned char macaddr[6];
|
464 |
|
|
// result = ax88796Read(TR);
|
465 |
|
|
|
466 |
|
|
// rprintf("Media State: ");
|
467 |
|
|
// if(!(result & AUTOD))
|
468 |
|
|
// rprintf("Autonegotiation\r\n");
|
469 |
|
|
// else if(result & RST_B)
|
470 |
|
|
// rprintf("PHY in Reset \r\n");
|
471 |
|
|
// else if(!(result & RST_10B))
|
472 |
|
|
// rprintf("10BASE-T \r\n");
|
473 |
|
|
// else if(!(result & RST_TXB))
|
474 |
|
|
// rprintf("100BASE-T \r\n");
|
475 |
|
|
|
476 |
|
|
rprintf("RevID: 0x%x\r\n", enc28j60Read(EREVID));
|
477 |
|
|
|
478 |
|
|
rprintfProgStrM("Cntrl: ECON1 ECON2 ESTAT EIR EIE\r\n");
|
479 |
|
|
rprintfProgStrM(" ");
|
480 |
|
|
rprintfu08(enc28j60Read(ECON1));
|
481 |
|
|
rprintfProgStrM(" ");
|
482 |
|
|
rprintfu08(enc28j60Read(ECON2));
|
483 |
|
|
rprintfProgStrM(" ");
|
484 |
|
|
rprintfu08(enc28j60Read(ESTAT));
|
485 |
|
|
rprintfProgStrM(" ");
|
486 |
|
|
rprintfu08(enc28j60Read(EIR));
|
487 |
|
|
rprintfProgStrM(" ");
|
488 |
|
|
rprintfu08(enc28j60Read(EIE));
|
489 |
|
|
rprintfCRLF();
|
490 |
|
|
|
491 |
|
|
rprintfProgStrM("MAC : MACON1 MACON2 MACON3 MACON4 MAC-Address\r\n");
|
492 |
|
|
rprintfProgStrM(" 0x");
|
493 |
|
|
rprintfu08(enc28j60Read(MACON1));
|
494 |
|
|
rprintfProgStrM(" 0x");
|
495 |
|
|
rprintfu08(enc28j60Read(MACON2));
|
496 |
|
|
rprintfProgStrM(" 0x");
|
497 |
|
|
rprintfu08(enc28j60Read(MACON3));
|
498 |
|
|
rprintfProgStrM(" 0x");
|
499 |
|
|
rprintfu08(enc28j60Read(MACON4));
|
500 |
|
|
rprintfProgStrM(" ");
|
501 |
|
|
rprintfu08(enc28j60Read(MAADR5));
|
502 |
|
|
rprintfu08(enc28j60Read(MAADR4));
|
503 |
|
|
rprintfu08(enc28j60Read(MAADR3));
|
504 |
|
|
rprintfu08(enc28j60Read(MAADR2));
|
505 |
|
|
rprintfu08(enc28j60Read(MAADR1));
|
506 |
|
|
rprintfu08(enc28j60Read(MAADR0));
|
507 |
|
|
rprintfCRLF();
|
508 |
|
|
|
509 |
|
|
rprintfProgStrM("Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\r\n");
|
510 |
|
|
rprintfProgStrM(" 0x");
|
511 |
|
|
rprintfu08(enc28j60Read(ERXSTH));
|
512 |
|
|
rprintfu08(enc28j60Read(ERXSTL));
|
513 |
|
|
rprintfProgStrM(" 0x");
|
514 |
|
|
rprintfu08(enc28j60Read(ERXNDH));
|
515 |
|
|
rprintfu08(enc28j60Read(ERXNDL));
|
516 |
|
|
rprintfProgStrM(" 0x");
|
517 |
|
|
rprintfu08(enc28j60Read(ERXWRPTH));
|
518 |
|
|
rprintfu08(enc28j60Read(ERXWRPTL));
|
519 |
|
|
rprintfProgStrM(" 0x");
|
520 |
|
|
rprintfu08(enc28j60Read(ERXRDPTH));
|
521 |
|
|
rprintfu08(enc28j60Read(ERXRDPTL));
|
522 |
|
|
rprintfProgStrM(" 0x");
|
523 |
|
|
rprintfu08(enc28j60Read(ERXFCON));
|
524 |
|
|
rprintfProgStrM(" 0x");
|
525 |
|
|
rprintfu08(enc28j60Read(EPKTCNT));
|
526 |
|
|
rprintfProgStrM(" 0x");
|
527 |
|
|
rprintfu08(enc28j60Read(MAMXFLH));
|
528 |
|
|
rprintfu08(enc28j60Read(MAMXFLL));
|
529 |
|
|
rprintfCRLF();
|
530 |
|
|
|
531 |
|
|
rprintfProgStrM("Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\r\n");
|
532 |
|
|
rprintfProgStrM(" 0x");
|
533 |
|
|
rprintfu08(enc28j60Read(ETXSTH));
|
534 |
|
|
rprintfu08(enc28j60Read(ETXSTL));
|
535 |
|
|
rprintfProgStrM(" 0x");
|
536 |
|
|
rprintfu08(enc28j60Read(ETXNDH));
|
537 |
|
|
rprintfu08(enc28j60Read(ETXNDL));
|
538 |
|
|
rprintfProgStrM(" 0x");
|
539 |
|
|
rprintfu08(enc28j60Read(MACLCON1));
|
540 |
|
|
rprintfProgStrM(" 0x");
|
541 |
|
|
rprintfu08(enc28j60Read(MACLCON2));
|
542 |
|
|
rprintfProgStrM(" 0x");
|
543 |
|
|
rprintfu08(enc28j60Read(MAPHSUP));
|
544 |
|
|
rprintfCRLF();
|
545 |
|
|
|
546 |
|
|
rprintfProgStrM("EREVID\r\n");
|
547 |
|
|
rprintfProgStrM(" 0x");
|
548 |
|
|
rprintfu08(enc28j60Read(EREVID));
|
549 |
|
|
|
550 |
|
|
delay_ms(25);
|
551 |
|
|
}
|
552 |
|
|
|
553 |
|
|
|
554 |
|
|
|