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atypic |
/*********************************************
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* vim:sw=8:ts=8:si:et
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* To use the above modeline in vim you must have "set modeline" in your .vimrc
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* Author: Guido Socher
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* Copyright: GPL V2
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*
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* Based on the enc28j60.c file from the AVRlib library by Pascal Stang.
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* For AVRlib See http://www.procyonengineering.com/
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* Used with explicit permission of Pascal Stang.
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*
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* Title: Microchip ENC28J60 Ethernet Interface Driver
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* Chip type : ATMEGA88 with ENC28J60
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*********************************************/
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#include <avr/io.h>
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#include "enc28j60.h"
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#include "enc28j60conf.h"
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#include <device.h>
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#include "global.h"
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static uint8_t Enc28j60Bank;
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static uint16_t NextPacketPtr;
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// set CS to 0 = active
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#define CSACTIVE ENC28J60_CONTROL_PORT&=~(1<<ENC28J60_CONTROL_CS)
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// set CS to 1 = passive
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#define CSPASSIVE ENC28J60_CONTROL_PORT|=(1<<ENC28J60_CONTROL_CS)
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//
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#define waitspi() while(!(SPSR&(1<<SPIF)))
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//struct igordev_data idata;
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int status;
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void nicSend(unsigned int len, uint8_t* packet)
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{
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enc28j60PacketSend(len, packet);
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}
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unsigned int nicPoll(unsigned int maxlen, unsigned char* packet)
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{
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return enc28j60PacketReceive(maxlen, packet);
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}
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uint8_t enc28j60ReadOp(uint8_t op, uint8_t address)
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{
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CSACTIVE;
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// issue read command
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SPDR = op | (address & ADDR_MASK);
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waitspi();
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// read data
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SPDR = 0x00;
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waitspi();
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// do dummy read if needed (for mac and mii, see datasheet page 29)
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if(address & 0x80)
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{
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SPDR = 0x00;
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waitspi();
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}
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// release CS
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CSPASSIVE;
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return(SPDR);
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}
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void enc28j60WriteOp(uint8_t op, uint8_t address, uint8_t data)
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{
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CSACTIVE;
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// issue write command
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SPDR = op | (address & ADDR_MASK);
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waitspi();
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// write data
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SPDR = data;
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waitspi();
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CSPASSIVE;
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}
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void enc28j60ReadBuffer(uint16_t len, uint8_t* data)
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{
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CSACTIVE;
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// issue read command
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SPDR = ENC28J60_READ_BUF_MEM;
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waitspi();
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while(len)
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{
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len--;
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// read data
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SPDR = 0x00;
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waitspi();
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*data = SPDR;
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data++;
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}
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// This is nonsence : *data='\0';
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CSPASSIVE;
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}
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void enc28j60WriteBuffer(uint16_t len, uint8_t* data)
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{
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CSACTIVE;
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// issue write command
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SPDR = ENC28J60_WRITE_BUF_MEM;
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waitspi();
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while(len)
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{
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len--;
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// write data
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SPDR = *data;
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data++;
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waitspi();
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}
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CSPASSIVE;
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}
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void enc28j60SetBank(uint8_t address)
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{
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// set the bank (if needed)
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if((address & BANK_MASK) != Enc28j60Bank)
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{
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// set the bank
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enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
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enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);
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Enc28j60Bank = (address & BANK_MASK);
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}
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}
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uint8_t enc28j60Read(uint8_t address)
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{
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// set the bank
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enc28j60SetBank(address);
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// do the read
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return enc28j60ReadOp(ENC28J60_READ_CTRL_REG, address);
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}
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void enc28j60Write(uint8_t address, uint8_t data)
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{
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// set the bank
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enc28j60SetBank(address);
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// do the write
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enc28j60WriteOp(ENC28J60_WRITE_CTRL_REG, address, data);
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}
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void enc28j60PhyWrite(uint8_t address, uint16_t data)
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{
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// set the PHY register address
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enc28j60Write(MIREGADR, address);
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// write the PHY data
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enc28j60Write(MIWRL, data);
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enc28j60Write(MIWRH, data>>8);
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// wait until the PHY write completes
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while(enc28j60Read(MISTAT) & MISTAT_BUSY){
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_delay_ms(0.015);
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}
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}
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//Run configure_spi() to setup the SPI port
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//before initializing the ethernet controller.
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void enc28j60Init()
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{
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//Setup is done in configure_spi(), so this has been commented out.
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/* // initialize I/O
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ENC28J60_CONTROL_DDR |= (1<<ENC28J60_CONTROL_CS);
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ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
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CSPASSIVE;
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// Disable powersaving
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PRR0 &= ~(1<<PRSPI);
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// setup SPI I/O pins
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// SCK should be low!
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ENC28J60_SPI_PORT &= ~(1<<ENC28J60_SPI_SCK);
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ENC28J60_SPI_DDR |= (1<<ENC28J60_SPI_SCK); // set SCK as output
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ENC28J60_SPI_DDR &= ~(1<<ENC28J60_SPI_MISO); // set MISO as input
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ENC28J60_SPI_DDR |= ~(1<<ENC28J60_SPI_MOSI);// set MOSI as output
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ENC28J60_SPI_PORT &= ~(1<<ENC28J60_SPI_MOSI); // set MOSI low
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ENC28J60_SPI_DDR |= ~(1<<ENC28J60_SPI_SS);
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// initialize SPI interface
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// master mode
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// select clock phase positive-going in middle of data
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// select clock phase
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// Data order MSB first
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// switch to f/4 2X = f/2 bitrate
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// No dual datarate
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SPCR = (1<<MSTR)|(0<<CPOL)|(0<<CPHA)|(0<<DORD)|(0<<SPR0)|(1<<SPR1)|(0<<SPI2X)|(1<<SPE);
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*/
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// perform system reset
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enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
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_delay_ms(50);
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// check CLKRDY bit to see if reset is complete
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// The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait.
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//while(!(enc28j60Read(ESTAT) & ESTAT_CLKRDY));
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// do bank 0 stuff
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// initialize receive buffer
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// 16-bit transfers, must write low byte first
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// set receive buffer start address
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NextPacketPtr = RXSTART_INIT;
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// Rx start
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enc28j60Write(ERXSTL, RXSTART_INIT&0xFF);
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enc28j60Write(ERXSTH, RXSTART_INIT>>8);
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// set receive pointer address
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enc28j60Write(ERXRDPTL, RXSTART_INIT&0xFF);
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enc28j60Write(ERXRDPTH, RXSTART_INIT>>8);
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// RX end
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enc28j60Write(ERXNDL, RXSTOP_INIT&0xFF);
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enc28j60Write(ERXNDH, RXSTOP_INIT>>8);
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// TX start
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enc28j60Write(ETXSTL, TXSTART_INIT&0xFF);
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enc28j60Write(ETXSTH, TXSTART_INIT>>8);
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// TX end
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enc28j60Write(ETXNDL, TXSTOP_INIT&0xFF);
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enc28j60Write(ETXNDH, TXSTOP_INIT>>8);
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// do bank 1 stuff, packet filter:
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// For broadcast packets we allow only ARP packtets
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// All other packets should be unicast only for our mac (MAADR)
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//
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// The pattern to match on is therefore
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// Type ETH.DST
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// ARP BROADCAST
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// 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
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// in binary these poitions are:11 0000 0011 1111
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// This is hex 303F->EPMM0=0x3f,EPMM1=0x30
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//enc28j60Write(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN);
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//enc28j60Write(EPMM0, 0x3f);
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//enc28j60Write(EPMM1, 0x30);
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//enc28j60Write(EPMCSL, 0xf9);
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//enc28j60Write(EPMCSH, 0xf7);
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enc28j60Write(ERXFCON, 0); //Disable packet filter
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//
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//
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// do bank 2 stuff
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// enable MAC receive
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enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
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// bring MAC out of reset
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enc28j60Write(MACON2, 0x00);
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// enable automatic padding to 60bytes and CRC operations
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enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
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// set inter-frame gap (non-back-to-back)
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enc28j60Write(MAIPGL, 0x12);
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enc28j60Write(MAIPGH, 0x0C);
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// set inter-frame gap (back-to-back)
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enc28j60Write(MABBIPG, 0x12);
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// Set the maximum packet size which the controller will accept
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// Do not send packets longer than MAX_FRAMELEN:
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enc28j60Write(MAMXFLL, MAX_FRAMELEN&0xFF);
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enc28j60Write(MAMXFLH, MAX_FRAMELEN>>8);
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// do bank 3 stuff
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// write MAC address
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// NOTE: MAC address in ENC28J60 is byte-backward
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enc28j60Write(MAADR5, ENC28J60_MAC0);
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enc28j60Write(MAADR4, ENC28J60_MAC1);
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enc28j60Write(MAADR3, ENC28J60_MAC2);
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enc28j60Write(MAADR2, ENC28J60_MAC3);
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enc28j60Write(MAADR1, ENC28J60_MAC4);
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enc28j60Write(MAADR0, ENC28J60_MAC5);
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// no loopback of transmitted frames
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enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS);
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// switch to bank 0
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enc28j60SetBank(ECON1);
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// enable interrutps
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//enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
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// enable packet reception
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enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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}
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// read the revision of the chip:
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uint8_t enc28j60getrev(void)
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{
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return(enc28j60Read(EREVID));
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}
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void enc28j60PacketSend(uint16_t len, uint8_t* packet)
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{
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// Set the write pointer to start of transmit buffer area
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enc28j60Write(EWRPTL, TXSTART_INIT&0xFF);
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enc28j60Write(EWRPTH, TXSTART_INIT>>8);
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// Set the TXND pointer to correspond to the packet size given
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enc28j60Write(ETXNDL, (TXSTART_INIT+len)&0xFF);
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enc28j60Write(ETXNDH, (TXSTART_INIT+len)>>8);
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// write per-packet control byte (0x00 means use macon3 settings)
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enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
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// copy the packet into the transmit buffer
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enc28j60WriteBuffer(len, packet);
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// send the contents of the transmit buffer onto the network
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enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
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// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
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if( (enc28j60Read(EIR) & EIR_TXERIF) ){
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enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
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}
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}
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void enc28j60PacketSendTwo(uint16_t len1, uint8_t* packet1, uint16_t len2, uint8_t* packet2)
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{
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//Errata: Transmit Logic reset
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enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
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enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
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// Set the write pointer to start of transmit buffer area
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enc28j60Write(EWRPTL, TXSTART_INIT&0xff);
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enc28j60Write(EWRPTH, TXSTART_INIT>>8);
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// Set the TXND pointer to correspond to the packet size given
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enc28j60Write(ETXNDL, (TXSTART_INIT+len1+len2));
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enc28j60Write(ETXNDH, (TXSTART_INIT+len1+len2)>>8);
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// write per-packet control byte
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enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
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// copy the packet into the transmit buffer
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enc28j60WriteBuffer(len1, packet1);
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if(len2>0) enc28j60WriteBuffer(len2, packet2);
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311 |
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// send the contents of the transmit buffer onto the network
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enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
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}
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314 |
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315 |
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// Gets a packet from the network receive buffer, if one is available.
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316 |
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// The packet will by headed by an ethernet header.
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317 |
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// maxlen The maximum acceptable length of a retrieved packet.
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318 |
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// packet Pointer where packet data should be stored.
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319 |
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// Returns: Packet length in bytes if a packet was retrieved, zero otherwise.
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320 |
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uint16_t enc28j60PacketReceive(uint16_t maxlen, uint8_t* packet)
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321 |
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{
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322 |
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uint16_t rxstat;
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323 |
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uint16_t len;
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324 |
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// check if a packet has been received and buffered
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325 |
|
|
//if( !(enc28j60Read(EIR) & EIR_PKTIF) ){
|
326 |
|
|
// The above does not work. See Rev. B4 Silicon Errata point 6.
|
327 |
|
|
if( enc28j60Read(EPKTCNT) ==0 ){
|
328 |
|
|
return(0);
|
329 |
|
|
}
|
330 |
|
|
|
331 |
|
|
// Set the read pointer to the start of the received packet
|
332 |
|
|
enc28j60Write(ERDPTL, (NextPacketPtr));
|
333 |
|
|
enc28j60Write(ERDPTH, (NextPacketPtr)>>8);
|
334 |
|
|
// read the next packet pointer
|
335 |
|
|
NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
|
336 |
|
|
NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
|
337 |
|
|
// read the packet length (see datasheet page 43)
|
338 |
|
|
len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
|
339 |
|
|
len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
|
340 |
|
|
len-=4; //remove the CRC count
|
341 |
|
|
// read the receive status (see datasheet page 43)
|
342 |
|
|
rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
|
343 |
|
|
rxstat |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
|
344 |
|
|
// limit retrieve length
|
345 |
|
|
if (len>maxlen-1){
|
346 |
|
|
len=maxlen-1;
|
347 |
|
|
}
|
348 |
|
|
// check CRC and symbol errors (see datasheet page 44, table 7-3):
|
349 |
|
|
// The ERXFCON.CRCEN is set by default. Normally we should not
|
350 |
|
|
// need to check this.
|
351 |
|
|
if ((rxstat & 0x80)==0){
|
352 |
|
|
// invalid
|
353 |
|
|
len=0;
|
354 |
|
|
}else{
|
355 |
|
|
// copy the packet from the receive buffer
|
356 |
|
|
enc28j60ReadBuffer(len, packet);
|
357 |
|
|
}
|
358 |
|
|
// Move the RX read pointer to the start of the next received packet
|
359 |
|
|
// This frees the memory we just read out
|
360 |
|
|
enc28j60Write(ERXRDPTL, (NextPacketPtr));
|
361 |
|
|
enc28j60Write(ERXRDPTH, (NextPacketPtr)>>8);
|
362 |
|
|
// decrement the packet counter indicate we are done with this packet
|
363 |
|
|
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
|
364 |
|
|
return(len);
|
365 |
|
|
}
|