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[/] [igor/] [trunk/] [processor/] [mc/] [alu.vhd] - Blame information for rev 2

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1 2 atypic
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.leval_package.all;
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entity alu is
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        port (
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                in_a            : in std_logic_vector(OBJECT_SIZE-1 downto 0);
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                in_b            : in std_logic_vector(OBJECT_SIZE-1 downto 0);
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                funct           : in std_logic_vector(FUNCT_SIZE-1 downto 0);
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                status  : out std_logic_vector(STATUS_REG_SIZE-1 downto 0);
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                output  : out std_logic_vector(OBJECT_SIZE-1 downto 0));
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end entity alu;
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architecture rtl of alu is
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-- DIVIDER IS TOO SLOW, DISABLED
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--      component divider is
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--              GENERIC(WIDTH_DIVID : Integer := 32;                      -- Width Dividend
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--                      WIDTH_DIVIS : Integer := 16);                     -- Width Divisor
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--              port(dividend  : in     std_logic_vector (WIDTH_DIVID-1 downto 0);
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--              divisor   : in     std_logic_vector (WIDTH_DIVIS-1 downto 0);
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--              quotient  : out    std_logic_vector (WIDTH_DIVID-1 downto 0);
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--              remainder : out    std_logic_vector (WIDTH_DIVIS-1 downto 0));
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--      end component divider;
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        signal mul_res : std_logic_vector(DATUM_SIZE*2-3 downto 0);
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        signal type_a : std_logic_vector(TYPE_SIZE-1 downto 0);
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        signal gc_flag_a : std_logic;
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        signal datum_a : std_logic_vector(DATUM_SIZE-1 downto 0);
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        signal type_b : std_logic_vector(TYPE_SIZE-1 downto 0);
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        signal gc_flag_b : std_logic;
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        signal datum_b : std_logic_vector(DATUM_SIZE-1 downto 0);
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        signal type_r : std_logic_vector(TYPE_SIZE-1 downto 0);
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        signal gc_flag_r : std_logic;
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        signal datum_r : std_logic_vector(DATUM_SIZE-1 downto 0);
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--      signal div_r : std_logic_vector(DATUM_SIZE-1 downto 0);
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--      signal mod_r : std_logic_vector(DATUM_SIZE-1 downto 0);
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--      signal fti_r : std_logic_vector(DATUM_SIZE-1 downto 0);
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--      signal itf_r : std_logic_vector(DATUM_SIZE-1 downto 0);
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--      signal fad_r : std_logic_vector(DATUM_SIZE-1 downto 0);
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--      signal fml_r : std_logic_vector(DATUM_SIZE-1 downto 0);
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--      signal fdv_r : std_logic_vector(DATUM_SIZE-1 downto 0);
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--      signal fti_v, fti_a : std_logic;
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--      signal fad_v, fad_u, fad_a : std_logic;
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--      signal fml_v, fml_u, fml_a : std_logic;
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--      signal fdv_v, fdv_u, fdv_a, fdv_zero : std_logic;
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begin
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--      divider_inst : divider
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--      generic map (26,26)
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--      port map (
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--              dividend => datum_a,
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--              divisor => datum_b,
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--              quotient => div_r,
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--              remainder => mod_r);
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--              
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        -- Decode inputs
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        type_a <= in_a(OBJECT_SIZE-1 downto 27);
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        gc_flag_a <= in_a(26);
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        datum_a <= in_a(25 downto 0);
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        type_b <= in_b(OBJECT_SIZE-1 downto 27);
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        gc_flag_b <= in_b(26);
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        datum_b <= in_b(25 downto 0);
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        -- SET STATUS FLAGS
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        -- Overflow
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        status(OVERFLOW) <= '0' when (mul_res(49 downto 25) = (mul_res(49 downto 25) xor mul_res(49 downto 25))) else '1';
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        -- negative
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        status(NEG) <= datum_r(25);
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        -- zero
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        status(ZERO) <= '1' when datum_r = (datum_r xor datum_r) else '0';
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        -- type error
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        status(TYP) <= '0' when type_a = type_b else '1';
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        -- io-error
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        status(IO) <= '0';
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        --unused
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        status(1) <= '0';
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        status(6) <= '0';
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        status(7) <= '0';
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        mul_res <= (datum_a(24 downto 0) * datum_b(24 downto 0));
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        -- set output to result
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        output <= type_r & gc_flag_r & datum_r;
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        process(funct, type_a, type_b, gc_flag_a, gc_flag_b, datum_a, datum_b, mul_res)
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        begin
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                type_r <= (others => '0');
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                gc_flag_r <= '0';
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                datum_r  <= (others => '0');
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                case funct is
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                        when ALU_ADD =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= datum_a + datum_b;
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                        when ALU_SUB =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= datum_a - datum_b;
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                        when ALU_MUL =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r(24 downto 0) <= mul_res(24 downto 0);
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                                datum_r(25) <= datum_a(25) xor datum_b(25);
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--                      when ALU_DIV =>
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--                              type_r <= type_a;
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--                              gc_flag_r <= gc_flag_a;
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--                              datum_r <= div_r;
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--                              
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--                      when ALU_MOD =>
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--                              type_r <= type_a;
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--                              gc_flag_r <= gc_flag_a;
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--                              datum_r <= mod_r;
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                        when ALU_AND =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= datum_a and datum_b;
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                        when ALU_OR =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= datum_a or datum_b;
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                        when ALU_XOR =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= datum_a xor datum_b;
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                        when ALU_GET_TYPE =>
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                                type_r <= DT_INT;
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                                gc_flag_r <= '0';
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                                datum_r(TYPE_SIZE - 1 downto 0) <= type_b;
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                                datum_r(DATUM_SIZE - 1 downto TYPE_SIZE) <= (others => '0');
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                        when ALU_SET_TYPE =>
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                                type_r <= datum_b(TYPE_SIZE-1 downto 0);
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                                gc_flag_r <= '0';
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                                datum_r <= datum_a;
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                        when ALU_SET_DATUM =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= datum_b;
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                        when ALU_SET_GC =>
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                                type_r <= type_a;
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                                gc_flag_r <= datum_b(0);
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                                datum_r <= datum_a;
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                        when ALU_GET_GC =>
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                                type_r <= DT_INT;
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                                gc_flag_r <= '0';
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                                datum_r(0) <= gc_flag_b;
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                                datum_r(DATUM_SIZE - 1 downto 1) <= (others => '0');
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                        when ALU_CPY =>
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                                type_r <= type_b;
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                                gc_flag_r <= gc_flag_b;
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                                datum_r <= datum_b;
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                        -- shift right
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                        when ALU_SR =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= std_logic_vector(shift_right(unsigned(datum_a),
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                                        to_integer(unsigned(datum_b))));
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                        -- shift left
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                        when ALU_SL =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= std_logic_vector(shift_left(unsigned(datum_a),
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                                        to_integer(unsigned(datum_b))));
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                        when ALU_CMP_DATUM =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= datum_a - datum_b;
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                        when ALU_CMP_TYPE =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= "000000000000000000000" & (type_a - type_b);
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                        when ALU_CMP_TYPE_IMM =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= "000000000000000000000" & (type_a - datum_b(TYPE_SIZE - 1 downto 0));
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                        when ALU_CMP_GC =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= "0000000000000000000000000"&(gc_flag_a xor gc_flag_b);
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                        when ALU_CMP_GC_IMM =>
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                                type_r <= type_a;
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                                gc_flag_r <= gc_flag_a;
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                                datum_r <= "0000000000000000000000000"&(gc_flag_a xor datum_b(0));
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                        when ALU_CMP =>
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                                if type_a = type_b and
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                                        datum_a = datum_b then -- we have equivalent objects
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                                        datum_r <= (others => '0');
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                                else
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                                        datum_r(DATUM_SIZE-1 downto DATUM_SIZE-4) <= "1111";
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                                        datum_r(DATUM_SIZE-5 downto 0) <= (others => '0'); -- not same
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                                end if;
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                        when others =>
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                                type_r <= (others => '0');
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                                gc_flag_r <= '0';
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                                datum_r  <= (others => '0');
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                end case;
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        end process;
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end rtl;

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