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[/] [igor/] [trunk/] [processor/] [mc/] [control.vhd] - Blame information for rev 2

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use work.leval_package.all;
 
entity control is
        port (
                clk                                     : in std_logic;
                rst                                     : in std_logic;
                -- status register
                status_in                       : in std_logic_vector(STATUS_REG_SIZE-1 downto 0);
                data_rdy                                : in std_logic; -- data ready on data bus signal
                sync                                    : in std_logic; -- AVR ready signal
                -- instruction signals
                opcode                          : in std_logic_vector(OPCODE_SIZE-1 downto 0);
                breakpoint                      : in std_logic;
                debug_en                                : in std_logic;
                break_mask                      : in std_logic_vector(STATUS_REG_SIZE-1 downto 0);
                break_flags                     : in std_logic_vector(STATUS_REG_SIZE-1 downto 0);
                indir_reg1                      : in std_logic;
                indir_reg2                      : in std_logic;
                -- scrath control signals
                write_reg_en            : out std_logic; -- enables writing of register file
                -- use address from indirect register-registers
                indir_reg1_sel          : out std_logic;
                indir_reg2_sel          : out std_logic;
                -- ALU
                alu_func                                : out std_logic_vector(FUNCT_SIZE-1 downto 0);
                alu_op1_sel                     : out std_logic; -- use r2 as first operand in ALU
                alu_op2_sel                     : out std_logic; -- when high use immidiate as second argument
                -- status register control line
                status_reg_w_en : out std_logic_vector(STATUS_REG_SIZE-1 downto 0);
                -- PC control
                pc_write_en                     : out std_logic; -- increment program counter
                branch_taken            : out std_logic; -- take branch
                -- memory control signals
                write                                   : out std_logic; -- write-signal
                read                                    : out std_logic; -- read-signal
                -- datapaths
                mem_to_reg_sel          : out std_logic; -- use databus instead of ALU result
                write_indir_addr_wr_en : out std_logic; -- udpate registers with indirect addresses
                state_out                       : out std_logic_vector(3 downto 0)); -- DEBUG SIGNAL
end entity;
 
architecture rtl of control is
        -- States
        type state_type is (st0_init,st1_fetch,st2_regfetch,st3_load_indir_regs,st4_load_indir_data,
                st5_execute,st6_wait_data,st7_wait_done,st8_io_done,st9_halt);
        signal state : state_type := st0_init;
        signal jump : boolean;
        signal stored : boolean := true; -- this is used only on LOAD operations to know if we
                                                                                                -- wrote result into register. So we can use the same
                                                                                                -- register for address and result
begin
 
        -- DECODE AND OUTPUT
        OUTPUT_DECODE: process (state,opcode,indir_reg1,indir_reg2,jump,stored,data_rdy)
        begin
                -- default values
                write_reg_en            <= '0'; -- disable register writing
                mem_to_reg_sel          <= '0'; -- use ALU's result
                alu_op1_sel             <= '0'; -- don't write result
                indir_reg1_sel          <= '0'; -- don't use indir-regs default
                indir_reg2_sel          <= '0';
                alu_func                                <= (others => '0');
                alu_op2_sel                     <= '0'; -- don't use immidiate default
                status_reg_w_en <= (others => '0'); -- don't write status register
                branch_taken            <= '0'; -- don't branch
                write                   <= '0';
                read                            <= '0';
                pc_write_en                     <= '0'; -- don't change PC
                write_indir_addr_wr_en <= '0';
                stored <= stored;
 
                case    (state) is
                        when st0_init =>
                                state_out <= X"0";
 
                        when st1_fetch =>
                                state_out <= X"1";
 
                        when st2_regfetch =>
                                -- do nothing, we're waiting for the registers to load
                                state_out <= X"2";
 
                        when st3_load_indir_regs =>
                                -- load the indirection registers with the current register-out values
                                state_out <= X"3";
                                write_indir_addr_wr_en <= '1';
                                 -- load indirect value
                                if indir_reg1 = '1' then
                                        indir_reg1_sel <= '1';
                                end if;
                                if indir_reg2 = '1' then
                                        indir_reg2_sel <= '1';
                                end if;
 
                        when st4_load_indir_data =>
                                -- do nothing
                                state_out <= X"4";
                                if indir_reg1 = '1' then
                                        indir_reg1_sel  <=      '1';
                                end if;
                                if      indir_reg2 = '1' then
                                        indir_reg2_sel  <=      '1';
                                end if;
 
                        when st5_execute =>
                                -- main execution state, sets signals according to input and state
                                state_out <= X"5";
                                status_reg_w_en <= (others => '1'); -- update status register on each operation
 
                                -- if we have load or store, we should wait with updating of PC
                                if (opcode = LOAD or opcode = STORE) then
                                        pc_write_en <= '0';
                                else
                                        pc_write_en <= '1';
                                end if;
 
                                -- indirect addressing
                                if indir_reg1 = '1' then
                                        indir_reg1_sel <= '1';
                                end if;
                                if indir_reg2 = '1' then
                                        indir_reg2_sel <= '1';
                                end if;
 
                                case opcode is
                                        -- Arithmetical / Logic functions
                                        when ADD =>
                                                alu_func <= ALU_ADD;
                                                write_reg_en <= '1';
 
                                        when SUBB =>
                                                alu_func <= ALU_SUB;
                                                write_reg_en <= '1';
 
                                        when MUL =>
                                                alu_func <= ALU_MUL;
                                                write_reg_en <= '1';
 
--                                      -- NOT IMPLEMENTED
--                                      when DIV =>
--                                              alu_func <= ALU_DIV;
--                                              write_reg_en <= '1';
--                                      when MODULO =>
--                                              alu_func <= ALU_MOD;
--                                              write_reg_en <= '1';
 
                                        when LAND =>
                                                alu_func <= ALU_AND;
                                                write_reg_en <= '1';
 
                                        when LOR =>
                                                alu_func <= ALU_OR;
                                                write_reg_en <= '1';
 
                                        when LXOR =>
                                                alu_func <= ALU_XOR;
                                                write_reg_en <= '1';
 
                                        when LOAD =>
                                                mem_to_reg_sel <= '1'; -- use data bus
                                                alu_func <= ALU_ADD;
                                                alu_op2_sel <= '1';
                                                alu_op1_sel <= '1';
                                                stored <= false;
 
                                        when STORE =>
                                                alu_func <= ALU_ADD;
                                                alu_op2_sel <= '1';
                                                alu_op1_sel <= '1';
                                                stored <= true;
 
                                        when BIDX =>
                                                if jump then
                                                        alu_func <= ALU_ADD;
                                                        branch_taken <= '1';
                                                        alu_op2_sel <= '1';
                                                end if;
 
                                        when GET_TYPE =>
                                                alu_func <= ALU_GET_TYPE;
                                                write_reg_en <= '1';
 
                                        when SET_TYPE =>
                                                alu_func <= ALU_SET_TYPE;
                                                write_reg_en <= '1';
 
                                        when SET_TYPE_IMM       =>
                                                alu_func <= ALU_SET_TYPE;
                                                write_reg_en <= '1';
                                                alu_op2_sel <= '1';
 
                                        when SET_DATUM =>
                                                alu_func <= ALU_SET_DATUM;
                                                write_reg_en <= '1';
 
                                        when SET_DATUM_IMM =>
                                                alu_func <= ALU_SET_DATUM;
                                                write_reg_en <= '1';
                                                alu_op2_sel <= '1';
 
                                        when SET_GC =>
                                                alu_func <= ALU_SET_GC;
                                                write_reg_en <= '1';
 
                                        when SET_GC_IMM =>
                                                alu_func <= ALU_SET_GC;
                                                write_reg_en <= '1';
                                                alu_op2_sel <= '1';
 
                                        when CPY =>
                                                alu_func <= ALU_CPY;
                                                write_reg_en <= '1';
 
                                        when CMP_TYPE =>
                                                alu_func <= ALU_CMP_TYPE;
 
                                        when CMP_TYPE_IMM =>
                                                alu_func <= ALU_CMP_TYPE_IMM;
                                                alu_op2_sel <= '1';
 
                                        when CMP_DATUM =>
                                                alu_func <= ALU_CMP_DATUM;
 
                                        when CMP_DATUM_IMM =>
                                                alu_func <= ALU_CMP_DATUM;
                                                alu_op2_sel <= '1';
 
                                        when CMP_GC =>
                                                alu_func <= ALU_CMP_GC;
 
                                        when CMP_GC_IMM =>
                                                alu_func <= ALU_CMP_GC_IMM;
                                                alu_op2_sel <= '1';
 
                                        when CMP =>
                                                alu_func <= ALU_CMP;
 
                                        when SHIFT_L =>
                                                alu_func <= ALU_SL;
                                                write_reg_en <= '1';
 
                                        when SHIFT_R =>
                                                alu_func <= ALU_SR;
                                                write_reg_en <= '1';
 
                                        when SETLED =>
                                                alu_func <= ALU_SETLED;
 
                                        when others =>
                                                -- unknown opcode, do nothing
                                                alu_func <= ALU_PASS;
                                        end case;
 
                        when st6_wait_data =>
                                -- HOLD load or store signals
                                state_out <= X"6";
                                if indir_reg1 = '1' then
                                        indir_reg1_sel <= '1';
                                end if;
                                if indir_reg2 = '1' then
                                        indir_reg2_sel <= '1';
                                end if;
 
                                alu_op2_sel <= '1'; -- use immediate value
                                alu_func <= ALU_ADD;  --calculate load/store address
                                alu_op1_sel <= '1'; -- use R2 with immidiate in ALU
 
                                if (opcode = LOAD) then
                                        mem_to_reg_sel <= '1'; -- load data from bus
                                        read <= '1'; -- set read control signal
                                        if data_rdy = '0' and stored = false then -- if data is not stored, but ready on the bus
                                                write_reg_en <= '1'; -- enable writing of the register
                                                stored <= true; -- remember that we stored data
                                        end if;
                                else -- means STORE
                                        stored <= true; -- we don't need to write anything in register memory
                                        write <= '1'; -- set write control signal
                                end if;
 
                        when st7_wait_done =>
                                -- remove read/write signal and wait till distanation unit clears ready control line
                                state_out <= X"7";
                                -- hold address values just to be sure
                                if indir_reg1 = '1' then
                                        indir_reg1_sel <= '1';
                                end if;
                                if indir_reg2 = '1' then
                                        indir_reg2_sel <= '1';
                                end if;
                                alu_op2_sel <= '1';
                                alu_func <= ALU_ADD;
                                alu_op1_sel <= '1';
 
                        when st8_io_done =>
                                -- one cycle to update PC
                                state_out <= X"8";
                                pc_write_en <= '1';
 
                        when st9_halt =>
                                -- HALT state (we can't get out of here unless reset)
                                state_out <= X"9";
 
                        when others =>
                                -- unknown state
                                state_out <= X"F";
                end case;
 
        end process;
 
        -- NEXT STATE FUNCTION
        NEXT_STATE_DECODE: process(clk)
        begin
        if rising_edge(clk) then
                if rst = '1' then
                        state <= st0_init;
                end if;
                case (state) is
                        when st0_init =>
                                if sync = '1' then
                                        state <= st1_fetch;
                                end if;
                        when st1_fetch =>
                                state <= st2_regfetch;
 
                        when st2_regfetch =>
                                if indir_reg1 = '1' or indir_reg2 = '1' then
                                        -- if we need to load indirect registers
                                        state <= st3_load_indir_regs;
                                else
                                        state <= st5_execute;
                                end if;
 
                        when st3_load_indir_regs =>
                                state <= st4_load_indir_data;
 
                        when st4_load_indir_data =>
                                state <= st5_execute;
 
                        when st5_execute =>
                                -- HALT conditions
                                if breakpoint = '1' or debug_en = '1' or opcode = HALT then
                                        state <= st9_halt;
                                -- LOAD/STORE
                                elsif opcode=LOAD or opcode = STORE then
                                        state <= st6_wait_data;
                                -- otherwise go to fetch next instruction
                                else
                                        state <= st1_fetch;
                                end if;
                        when st6_wait_data =>
                                if data_rdy = '0' and stored = true then
                                        state <= st7_wait_done;
                                end if;
 
                        when st7_wait_done =>
                                if data_rdy = '1' then
                                        state <= st8_io_done;
                                end if;
 
                        when st8_io_done =>
                                        state <= st1_fetch;
 
                        when st9_halt =>
                                -- We halt, program is over.
                end case;
        end if;
        end process;
 
        update_branch_evaluator : process(clk)
        begin
                if rising_edge(clk) then
                        -- compare status register with branch flags, filtered by branch mask
                        if (status_in and break_mask) = (break_flags and break_mask) then
                                jump <= true;
                        else
                                jump <= false;
                        end if;
                end if;
        end process;
end rtl;

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[/] [igor/] [trunk/] [processor/] [mc/] [control.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atypic	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.numeric_std.all;`
4			`use ieee.std_logic_signed.all;`
5			`use work.leval_package.all;`
6
7			`entity control is`
8			`port (`
9			`clk : in std_logic;`
10			`rst : in std_logic;`
11			`-- status register`
12			`status_in : in std_logic_vector(STATUS_REG_SIZE-1 downto 0);`
13			`data_rdy : in std_logic; -- data ready on data bus signal`
14			`sync : in std_logic; -- AVR ready signal`
15			`-- instruction signals`
16			`opcode : in std_logic_vector(OPCODE_SIZE-1 downto 0);`
17			`breakpoint : in std_logic;`
18			`debug_en : in std_logic;`
19			`break_mask : in std_logic_vector(STATUS_REG_SIZE-1 downto 0);`
20			`break_flags : in std_logic_vector(STATUS_REG_SIZE-1 downto 0);`
21			`indir_reg1 : in std_logic;`
22			`indir_reg2 : in std_logic;`
23			`-- scrath control signals`
24			`write_reg_en : out std_logic; -- enables writing of register file`
25			`-- use address from indirect register-registers`
26			`indir_reg1_sel : out std_logic;`
27			`indir_reg2_sel : out std_logic;`
28			`-- ALU`
29			`alu_func : out std_logic_vector(FUNCT_SIZE-1 downto 0);`
30			`alu_op1_sel : out std_logic; -- use r2 as first operand in ALU`
31			`alu_op2_sel : out std_logic; -- when high use immidiate as second argument`
32			`-- status register control line`
33			`status_reg_w_en : out std_logic_vector(STATUS_REG_SIZE-1 downto 0);`
34			`-- PC control`
35			`pc_write_en : out std_logic; -- increment program counter`
36			`branch_taken : out std_logic; -- take branch`
37			`-- memory control signals`
38			`write : out std_logic; -- write-signal`
39			`read : out std_logic; -- read-signal`
40			`-- datapaths`
41			`mem_to_reg_sel : out std_logic; -- use databus instead of ALU result`
42			`write_indir_addr_wr_en : out std_logic; -- udpate registers with indirect addresses`
43			`state_out : out std_logic_vector(3 downto 0)); -- DEBUG SIGNAL`
44			`end entity;`
45
46			`architecture rtl of control is`
47			`-- States`
48			`type state_type is (st0_init,st1_fetch,st2_regfetch,st3_load_indir_regs,st4_load_indir_data,`
49			`st5_execute,st6_wait_data,st7_wait_done,st8_io_done,st9_halt);`
50			`signal state : state_type := st0_init;`
51			`signal jump : boolean;`
52			`signal stored : boolean := true; -- this is used only on LOAD operations to know if we`
53			`-- wrote result into register. So we can use the same`
54			`-- register for address and result`
55			`begin`
56
57			`-- DECODE AND OUTPUT`
58			`OUTPUT_DECODE: process (state,opcode,indir_reg1,indir_reg2,jump,stored,data_rdy)`
59			`begin`
60			`-- default values`
61			`write_reg_en <= '0'; -- disable register writing`
62			`mem_to_reg_sel <= '0'; -- use ALU's result`
63			`alu_op1_sel <= '0'; -- don't write result`
64			`indir_reg1_sel <= '0'; -- don't use indir-regs default`
65			`indir_reg2_sel <= '0';`
66			`alu_func <= (others => '0');`
67			`alu_op2_sel <= '0'; -- don't use immidiate default`
68			`status_reg_w_en <= (others => '0'); -- don't write status register`
69			`branch_taken <= '0'; -- don't branch`
70			`write <= '0';`
71			`read <= '0';`
72			`pc_write_en <= '0'; -- don't change PC`
73			`write_indir_addr_wr_en <= '0';`
74			`stored <= stored;`
75
76			`case (state) is`
77			`when st0_init =>`
78			`state_out <= X"0";`
79
80			`when st1_fetch =>`
81			`state_out <= X"1";`
82
83			`when st2_regfetch =>`
84			`-- do nothing, we're waiting for the registers to load`
85			`state_out <= X"2";`
86
87			`when st3_load_indir_regs =>`
88			`-- load the indirection registers with the current register-out values`
89			`state_out <= X"3";`
90			`write_indir_addr_wr_en <= '1';`
91			`-- load indirect value`
92			`if indir_reg1 = '1' then`
93			`indir_reg1_sel <= '1';`
94			`end if;`
95			`if indir_reg2 = '1' then`
96			`indir_reg2_sel <= '1';`
97			`end if;`
98
99			`when st4_load_indir_data =>`
100			`-- do nothing`
101			`state_out <= X"4";`
102			`if indir_reg1 = '1' then`
103			`indir_reg1_sel <= '1';`
104			`end if;`
105			`if indir_reg2 = '1' then`
106			`indir_reg2_sel <= '1';`
107			`end if;`
108
109			`when st5_execute =>`
110			`-- main execution state, sets signals according to input and state`
111			`state_out <= X"5";`
112			`status_reg_w_en <= (others => '1'); -- update status register on each operation`
113
114			`-- if we have load or store, we should wait with updating of PC`
115			`if (opcode = LOAD or opcode = STORE) then`
116			`pc_write_en <= '0';`
117			`else`
118			`pc_write_en <= '1';`
119			`end if;`
120
121			`-- indirect addressing`
122			`if indir_reg1 = '1' then`
123			`indir_reg1_sel <= '1';`
124			`end if;`
125			`if indir_reg2 = '1' then`
126			`indir_reg2_sel <= '1';`
127			`end if;`
128
129			`case opcode is`
130			`-- Arithmetical / Logic functions`
131			`when ADD =>`
132			`alu_func <= ALU_ADD;`
133			`write_reg_en <= '1';`
134
135			`when SUBB =>`
136			`alu_func <= ALU_SUB;`
137			`write_reg_en <= '1';`
138
139			`when MUL =>`
140			`alu_func <= ALU_MUL;`
141			`write_reg_en <= '1';`
142
143			`-- -- NOT IMPLEMENTED`
144			`-- when DIV =>`
145			`-- alu_func <= ALU_DIV;`
146			`-- write_reg_en <= '1';`
147			`-- when MODULO =>`
148			`-- alu_func <= ALU_MOD;`
149			`-- write_reg_en <= '1';`
150
151			`when LAND =>`
152			`alu_func <= ALU_AND;`
153			`write_reg_en <= '1';`
154
155			`when LOR =>`
156			`alu_func <= ALU_OR;`
157			`write_reg_en <= '1';`
158
159			`when LXOR =>`
160			`alu_func <= ALU_XOR;`
161			`write_reg_en <= '1';`
162
163			`when LOAD =>`
164			`mem_to_reg_sel <= '1'; -- use data bus`
165			`alu_func <= ALU_ADD;`
166			`alu_op2_sel <= '1';`
167			`alu_op1_sel <= '1';`
168			`stored <= false;`
169
170			`when STORE =>`
171			`alu_func <= ALU_ADD;`
172			`alu_op2_sel <= '1';`
173			`alu_op1_sel <= '1';`
174			`stored <= true;`
175
176			`when BIDX =>`
177			`if jump then`
178			`alu_func <= ALU_ADD;`
179			`branch_taken <= '1';`
180			`alu_op2_sel <= '1';`
181			`end if;`
182
183			`when GET_TYPE =>`
184			`alu_func <= ALU_GET_TYPE;`
185			`write_reg_en <= '1';`
186
187			`when SET_TYPE =>`
188			`alu_func <= ALU_SET_TYPE;`
189			`write_reg_en <= '1';`
190
191			`when SET_TYPE_IMM =>`
192			`alu_func <= ALU_SET_TYPE;`
193			`write_reg_en <= '1';`
194			`alu_op2_sel <= '1';`
195
196			`when SET_DATUM =>`
197			`alu_func <= ALU_SET_DATUM;`
198			`write_reg_en <= '1';`
199
200			`when SET_DATUM_IMM =>`
201			`alu_func <= ALU_SET_DATUM;`
202			`write_reg_en <= '1';`
203			`alu_op2_sel <= '1';`
204
205			`when SET_GC =>`
206			`alu_func <= ALU_SET_GC;`
207			`write_reg_en <= '1';`
208
209			`when SET_GC_IMM =>`
210			`alu_func <= ALU_SET_GC;`
211			`write_reg_en <= '1';`
212			`alu_op2_sel <= '1';`
213
214			`when CPY =>`
215			`alu_func <= ALU_CPY;`
216			`write_reg_en <= '1';`
217
218			`when CMP_TYPE =>`
219			`alu_func <= ALU_CMP_TYPE;`
220
221			`when CMP_TYPE_IMM =>`
222			`alu_func <= ALU_CMP_TYPE_IMM;`
223			`alu_op2_sel <= '1';`
224
225			`when CMP_DATUM =>`
226			`alu_func <= ALU_CMP_DATUM;`
227
228			`when CMP_DATUM_IMM =>`
229			`alu_func <= ALU_CMP_DATUM;`
230			`alu_op2_sel <= '1';`
231
232			`when CMP_GC =>`
233			`alu_func <= ALU_CMP_GC;`
234
235			`when CMP_GC_IMM =>`
236			`alu_func <= ALU_CMP_GC_IMM;`
237			`alu_op2_sel <= '1';`
238
239			`when CMP =>`
240			`alu_func <= ALU_CMP;`
241
242			`when SHIFT_L =>`
243			`alu_func <= ALU_SL;`
244			`write_reg_en <= '1';`
245
246			`when SHIFT_R =>`
247			`alu_func <= ALU_SR;`
248			`write_reg_en <= '1';`
249
250			`when SETLED =>`
251			`alu_func <= ALU_SETLED;`
252
253			`when others =>`
254			`-- unknown opcode, do nothing`
255			`alu_func <= ALU_PASS;`
256			`end case;`
257
258			`when st6_wait_data =>`
259			`-- HOLD load or store signals`
260			`state_out <= X"6";`
261			`if indir_reg1 = '1' then`
262			`indir_reg1_sel <= '1';`
263			`end if;`
264			`if indir_reg2 = '1' then`
265			`indir_reg2_sel <= '1';`
266			`end if;`
267
268			`alu_op2_sel <= '1'; -- use immediate value`
269			`alu_func <= ALU_ADD; --calculate load/store address`
270			`alu_op1_sel <= '1'; -- use R2 with immidiate in ALU`
271
272			`if (opcode = LOAD) then`
273			`mem_to_reg_sel <= '1'; -- load data from bus`
274			`read <= '1'; -- set read control signal`
275			`if data_rdy = '0' and stored = false then -- if data is not stored, but ready on the bus`
276			`write_reg_en <= '1'; -- enable writing of the register`
277			`stored <= true; -- remember that we stored data`
278			`end if;`
279			`else -- means STORE`
280			`stored <= true; -- we don't need to write anything in register memory`
281			`write <= '1'; -- set write control signal`
282			`end if;`
283
284			`when st7_wait_done =>`
285			`-- remove read/write signal and wait till distanation unit clears ready control line`
286			`state_out <= X"7";`
287			`-- hold address values just to be sure`
288			`if indir_reg1 = '1' then`
289			`indir_reg1_sel <= '1';`
290			`end if;`
291			`if indir_reg2 = '1' then`
292			`indir_reg2_sel <= '1';`
293			`end if;`
294			`alu_op2_sel <= '1';`
295			`alu_func <= ALU_ADD;`
296			`alu_op1_sel <= '1';`
297
298			`when st8_io_done =>`
299			`-- one cycle to update PC`
300			`state_out <= X"8";`
301			`pc_write_en <= '1';`
302
303			`when st9_halt =>`
304			`-- HALT state (we can't get out of here unless reset)`
305			`state_out <= X"9";`
306
307			`when others =>`
308			`-- unknown state`
309			`state_out <= X"F";`
310			`end case;`
311
312			`end process;`
313
314			`-- NEXT STATE FUNCTION`
315			`NEXT_STATE_DECODE: process(clk)`
316			`begin`
317			`if rising_edge(clk) then`
318			`if rst = '1' then`
319			`state <= st0_init;`
320			`end if;`
321			`case (state) is`
322			`when st0_init =>`
323			`if sync = '1' then`
324			`state <= st1_fetch;`
325			`end if;`
326			`when st1_fetch =>`
327			`state <= st2_regfetch;`
328
329			`when st2_regfetch =>`
330			`if indir_reg1 = '1' or indir_reg2 = '1' then`
331			`-- if we need to load indirect registers`
332			`state <= st3_load_indir_regs;`
333			`else`
334			`state <= st5_execute;`
335			`end if;`
336
337			`when st3_load_indir_regs =>`
338			`state <= st4_load_indir_data;`
339
340			`when st4_load_indir_data =>`
341			`state <= st5_execute;`
342
343			`when st5_execute =>`
344			`-- HALT conditions`
345			`if breakpoint = '1' or debug_en = '1' or opcode = HALT then`
346			`state <= st9_halt;`
347			`-- LOAD/STORE`
348			`elsif opcode=LOAD or opcode = STORE then`
349			`state <= st6_wait_data;`
350			`-- otherwise go to fetch next instruction`
351			`else`
352			`state <= st1_fetch;`
353			`end if;`
354			`when st6_wait_data =>`
355			`if data_rdy = '0' and stored = true then`
356			`state <= st7_wait_done;`
357			`end if;`
358
359			`when st7_wait_done =>`
360			`if data_rdy = '1' then`
361			`state <= st8_io_done;`
362			`end if;`
363
364			`when st8_io_done =>`
365			`state <= st1_fetch;`
366
367			`when st9_halt =>`
368			`-- We halt, program is over.`
369			`end case;`
370			`end if;`
371			`end process;`
372
373			`update_branch_evaluator : process(clk)`
374			`begin`
375			`if rising_edge(clk) then`
376			`-- compare status register with branch flags, filtered by branch mask`
377			`if (status_in and break_mask) = (break_flags and break_mask) then`
378			`jump <= true;`
379			`else`
380			`jump <= false;`
381			`end if;`
382			`end if;`
383			`end process;`
384			`end rtl;`