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[/] [igor/] [trunk/] [processor/] [mc/] [inst_mem.vhd] - Blame information for rev 2

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1 2 atypic
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-- Desc: Asynch ROM
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-- Author: Odd Rune
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.leval_package.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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entity inst_mem is
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    generic ( memsize, addrbits, databits  : integer;
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              initfile : string);
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        port (
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                clk : in std_logic;
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                addr : in std_logic_vector(addrbits - 1 downto 0);
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                dout : out std_logic_vector(databits - 1 downto 0);
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                din : in std_logic_vector(databits - 1 downto 0);
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                we : in std_logic
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        );
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end entity inst_mem;
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architecture behav of inst_mem is
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type rom_type is array(0 to memsize) of bit_vector(databits - 1
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downto 0);
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impure function init_rom(filename : in string) return rom_type is
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        file romfile : text is in filename;
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        variable li : line;
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        variable ROM : rom_type;
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        begin
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                for i in rom_type'range loop
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                        readline(romfile, li);
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                        read(li, ROM(i));
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                end loop;
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        return ROM;
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end function;
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signal ROM : rom_type := init_rom(initfile);
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signal read_reg : std_logic_vector(addrbits - 1 downto 0);
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begin
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        process(clk,addr)
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        begin
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                if rising_edge(clk) then
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                        if we = '1' then
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                                ROM(to_integer(unsigned(addr))) <= to_bitvector(din);
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                        end if;
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                        read_reg <= addr;
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                end if;
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        end process;
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        dout <= to_stdlogicvector(ROM(to_integer(unsigned(read_reg))));
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end architecture behav;

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