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[/] [igor/] [trunk/] [processor/] [mc/] [p_leval.vhd] - Blame information for rev 2

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1 2 atypic 
-------------------------------------------------------------------------------
2 
--      LEVAL   TYPES
3 
-------------------------------------------------------------------------------
4 
--      Package defines types   for     the     LevaL   CPU.
5 
-------------------------------------------------------------------------------
6 
--      Created:        28th    of      August  2008    [lykkebo]
7 
-------------------------------------------------------------------------------
8 
library ieee;
9 
use     ieee.std_logic_1164.all,        ieee.numeric_std.all;
10 
 
11 
package leval_package   is
12 
        --      CLEANING        UP      --
13 
        constant        WORD_SIZE                               :       integer :=      32;             --      Size    of      general word
14 
        constant        ADDR_SIZE                               :       integer :=      26;             --      Address bus     size
15 
        constant        SCRATCH_SIZE                    :       integer :=      1024;   --      Number  of      registers       in      scratch memory
16 
        constant        SCRATCH_ADDR_SIZE               :       integer :=      10;             --      Bus     size    for     register        address
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        constant        STATUS_REG_SIZE         :       integer :=      8;              --      size    of      stat.   reg
18 
        --      microcode
19 
        constant        MC_ADDR_SIZE                    :       integer :=      13;             --      Microcode       memory  address bus     size
20 
        constant        MC_INSTR_SIZE                   :       integer :=      48;             --      Microcode       instruction     size
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        constant        OPCODE_SIZE                             :       integer :=      6;
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        constant        TYPE_SIZE               :       integer         :=      5;
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        constant        REG1_S                                  :       integer :=      39;
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        constant        REG1_E                                  :       integer :=      29;
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        constant        REG2_S                                  :       integer :=      28;
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        constant        REG2_E                                  :       integer :=      18;
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        constant        REG3_S                                  :       integer :=      17;
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        constant        REG3_E                                  :       integer :=      7;
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        --      nR:     47      46      45      44      43      42      41      40      39      38      37      36      35      34      33      32      31      30      29      28      27      26      25      24      23      22      21      20      19      18      17      16      15      14      13      12      11      10      09      08      07      06      05      04      03      02      01      00
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        --      1R:     OP      OP      OP      OP      OP      OP      DE      BP      R1      R1      R1      R1      R1      R1      R1      R1      R1      R1      R1      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM
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        --      2R:     OP      OP      OP      OP      OP      OP      DE      BP      R1      R1      R1      R1      R1      R1      R1      R1      R1      R1      R1      R2      R2      R2      R2      R2      R2      R2      R2      R2      R2      R2      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM      IM
32 
        --      Branch  instructions
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        --      0R:     OP      OP      OP      OP      OP      OP      DE      BP      --      --      --      --      --      --      --      --      --      --      --      MK      MK      MK      MK      MK      MK      MK MK FG        FG      FG      FG      FG      FG      FG FG AD        AD      AD      AD      AD      AD      AD      AD      AD      AD      AD      AD      AD
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        --      1R:     OP      OP      OP      OP      OP      OP      DE      BP      R1      R1      R1      R1      R1      R1      R1      R1      R1      R1      R1      MK MK   MK      MK      MK      MK      MK      MK      FG      FG      FG      FG      FG      FG      FG FG AD        AD      AD      AD      AD      AD      AD      AD      AD      AD      AD      AD      AD
35 
 
36 
        -- Status flags
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        constant ZERO                           : integer := 3;
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        constant TYP                            : integer := 4;
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        constant OVERFLOW                       : integer := 0;
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        constant NEG                            : integer := 2;
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        constant IO                                     : integer := 5;
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43 
        --      ALU     operations
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        constant        ALU_PASS                        :       std_logic_vector(5 downto 0)     :=      "000000";
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        constant        ALU_ADD                 :       std_logic_vector(5 downto 0)     :=      "000001";
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        constant ALU_GET_TYPE   :       std_logic_vector(5 downto 0)     := "000010";
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        constant ALU_SET_TYPE   :       std_logic_vector(5 downto 0)     := "000011";
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        constant ALU_SET_DATUM  :       std_logic_vector(5 downto 0)     := "000100";
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        constant ALU_GET_DATUM  :       std_logic_vector(5 downto 0) := "000101";
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        constant ALU_SET_GC             :       std_logic_vector(5 downto 0)     := "001110";
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        constant ALU_GET_GC             :       std_logic_vector(5 downto 0)     := "000110";
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        constant ALU_SUB                        :       std_logic_vector(5 downto 0) := "000111";
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        constant ALU_CMP_TYPE   :       std_logic_vector(5 downto 0) := "001000";
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        constant        ALU_AND                 :       std_logic_vector(5 downto 0)     :=      "001001";
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        constant        ALU_OR                  :       std_logic_vector(5 downto 0)     :=      "001010";
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        constant        ALU_XOR                 :       std_logic_vector(5 downto 0)     :=      "001011";
57 
        constant        ALU_MUL                 :       std_logic_vector(5 downto 0)     :=      "001100";
58 
        constant        ALU_DIV                 :       std_logic_vector(5 downto 0)     :=      "001101";
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        constant ALU_MOD                        :  std_logic_vector(5 downto 0) :=  "001111";
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        constant ALU_SL                 : std_logic_Vector(5 downto 0) :=   "010000";
61 
        constant ALU_SR                 : std_logic_Vector(5 downto 0) :=   "010001";
62 
        constant ALU_SETLED             : std_logic_Vector(5 downto 0) :=   "010010";
63 
 
64 
        --      opcodes
65 
        -- compare operations
66 
        constant ALU_CMP_DATUM          : std_logic_vector(5 downto 0) := "010111";
67 
        constant ALU_CMP_GC                     : std_logic_vector(5 downto 0) := "011111";
68 
        constant ALU_CMP                                : std_logic_vector(5 downto 0) := "100000";
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        constant ALU_CMP_TYPE_IMM       : std_logic_vector(5 downto 0) := "010010";
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        constant ALU_CMP_DATUM_IMM : std_logic_vector(5 downto 0) := "010011";
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        constant ALU_CMP_GC_IMM         : std_logic_vector(5 downto 0) := "010100";
72 
        -- set operation
73 
        constant        ALU_CPY                 :       std_logic_vector(5 downto 0)     :=      "010101";
74 
 
75 
 
76 
  -- system operations
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        constant        NOP                     :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "000000";
78 
        constant        HALT                    :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "000001";
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        --      integer instructions
80 
        constant        ADD                     :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "000010";
81 
        constant        SUBB                    :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "000011";
82 
        constant        MUL                     :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "000100";
83 
        constant        DIV                     :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "000101";
84 
        constant        MODULO          :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "001011";
85 
        constant        SHIFT_L         :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "001010";
86 
        constant        SHIFT_R         :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "001100";
87 
        --      logical instructions
88 
        constant        LAND                    :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "000110";
89 
        constant        LOR                     :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "000111";
90 
        constant        LXOR                    :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "001000";
91 
        --      memory  instructions
92 
        constant        LOAD                    :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "010000";
93 
        constant        STORE                   :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "010001";
94 
        --      branch  instructions
95 
        constant        BIDX                    :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "010110";
96 
        --      data    manipulation
97 
        constant        GET_TYPE                :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "100000";
98 
        constant        SET_TYPE                :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "100001";
99 
        constant        SET_DATUM       :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "100011";
100 
        constant        GET_GC          :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "100101";
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        constant        SET_GC          :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "100110";
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        constant        CPY                     :       std_logic_vector(OPCODE_SIZE-1 downto 0) := "101000";
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        constant        SET_TYPE_IMM :  std_logic_vector(OPCODE_SIZE-1 downto 0) := "100010";
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        constant        SET_DATUM_IMM:  std_logic_vector(OPCODE_SIZE-1 downto 0) := "100100";
105 
        constant        SET_GC_IMM      : std_logic_vector(OPCODE_SIZE-1 downto 0)       :=      "100111";
106 
        --      compare functions
107 
        constant        CMP_TYPE                :       std_logic_vector(OPCODE_SIZE-1 downto 0) :=      "101001";
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        constant        CMP_TYPE_IMM:   std_logic_vector(OPCODE_SIZE-1 downto 0) :=      "101010";
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        constant        CMP_DATUM       :       std_logic_vector(OPCODE_SIZE-1 downto 0) :=      "101011";
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        constant        CMP_DATUM_IMM:  std_logic_vector(OPCODE_SIZE-1 downto 0) :=      "101100";
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        constant        CMP_GC          :       std_logic_vector(OPCODE_SIZE-1 downto 0) :=      "101101";
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        constant        CMP_GC_IMM      :       std_logic_vector(OPCODE_SIZE-1 downto 0) :=      "101110";
113 
        constant        CMP                     :       std_logic_vector(OPCODE_SIZE-1 downto 0) :=      "101111";
114 
        constant        SETLED          :       std_logic_vector(OPCODE_SIZE-1 downto 0) :=      "111111";
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        -- status masks
116 
        constant SM_INT : std_logic_vector(STATUS_REG_SIZE-1 downto 0) := "11110110";
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        constant SM_LOG : std_logic_vector(STATUS_REG_SIZE-1 downto 0) := "11000110";
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        constant SM_FPO : std_logic_vector(STATUS_REG_SIZE-1 downto 0) := "11111110";
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        constant SM_SYS : std_logic_vector(STATUS_REG_SIZE-1 downto 0) := "00000000";
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  constant SM_MEM : std_logic_vector(STATUS_REG_SIZE-1 downto 0) := "00000110";
121 
        constant SM_BR  : std_logic_vector(STATUS_REG_SIZE-1 downto 0) := "00000000";
122 
        constant SM_SGO : std_logic_vector(STATUS_REG_SIZE-1 downto 0) := "00000000"; -- set get operations
123 
--constant SM_CMP : std_logic_vector(STATUS_REG_SIZE-1 downto 0) := "11111110";
124 
 
125 
        -- data types
126 
        constant DT_NONE     : std_logic_vector(TYPE_SIZE-1 downto 0) := "00000";
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        constant DT_INT      : std_logic_vector(TYPE_SIZE-1 downto 0) := "00001";
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        constant DT_FLOAT    : std_logic_vector(TYPE_SIZE-1 downto 0) := "00010";
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        constant DT_CONS     : std_logic_vector(TYPE_SIZE-1 downto 0) := "00011";
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        constant DT_SNOC     : std_logic_vector(TYPE_SIZE-1 downto 0) := "00100";
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        constant DT_PTR      : std_logic_vector(TYPE_SIZE-1 downto 0) := "00101";
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        constant DT_ARRAY    : std_logic_vector(TYPE_SIZE-1 downto 0) := "00110";
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        constant DT_NIL      : std_logic_vector(TYPE_SIZE-1 downto 0) := "00111";
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        constant DT_T        : std_logic_vector(TYPE_SIZE-1 downto 0) := "01000";
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        constant DT_CHAR     : std_logic_vector(TYPE_SIZE-1 downto 0) := "01001";
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        constant DT_SYMBOL   : std_logic_vector(TYPE_SIZE-1 downto 0) := "01010";
137 
        constant DT_FUNCTION : std_logic_vector(TYPE_SIZE-1 downto 0) := "01011";
138 
 
139 
 
140 
        constant        IMM_SIZE                        :       integer :=10;
141 
        --      Constants       for     internal        typing
142 
        constant        OBJECT_SIZE             :       integer         :=      32;
143 
        constant        DATUM_SIZE              :       integer         :=      26;
144 
        constant        GC_SIZE                 :       integer         :=      1;
145 
        constant TYPE_START             :       integer         := OBJECT_SIZE - TYPE_SIZE;
146 
        constant GC_BIT                 :       integer         := 26;
147 
 
148 
        --      Typing  ...     types,  uhrm.
149 
        subtype object  is      std_logic_vector(OBJECT_SIZE    -       1 downto 0);
150 
        subtype object_type     is      std_logic_vector(TYPE_SIZE      -       1 downto 0);
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        subtype object_datum    is      std_logic_vector(DATUM_SIZE     -       1 downto 0);
152 
        subtype object_gc       is      std_logic_vector(GC_SIZE        -       1 downto 0);
153 
 
154 
        --      Type    constants
155 
        constant        TYPE_INT                        :       object_type             :=      "00010";
156 
 
157 
        --      Garbage collection      constants
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        constant        GC_TRUE                 :       object_gc               :=      "1";
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        constant        GC_FALSE                        :       object_gc               :=      "0";
160 
        --      General constants
161 
        constant        GENERATE_TRACE  :       boolean         :=      false;
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        constant        MC_ROM_SIZE             :       integer         :=      16384;  --      instruction     mem
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        constant        SCRATCH_MEM_SIZE        :       integer         :=      1024;   --      size    of      scratch
164 
 
165 
 
166 
        --      Instruction     word    constants
167 
        constant        IN_OP_SIZE              :       integer         :=      6;
168 
        constant        FUNCT_SIZE              :       integer :=6;    --      Size    of      function        word    for     ALU
169 
        constant        BUS_SIZE                        :       integer :=      32;
170 
        constant        SCRATCH_DEPTH   :       integer         :=      10;
171 
 
172 
        --      Clock   freq    in      MHz
173 
        constant        LEVAL_FREQ              :       std_logic_vector(7 downto 0)     :=      X"40";
174 
 
175 
        --constant MEMORY_LATENCY : integer := 52; --ms
176 
 
177 
 
178 
        --      Types   relating        to      micro-code
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        subtype mc_inst is      std_logic_vector(MC_INSTR_SIZE  -       1 downto 0);     --      instructions
180 
 
181 
        subtype mc_addr is      natural range   0        to      MC_ROM_SIZE;
182 
        type    mc_rom  is      array(mc_addr)  of      mc_inst;
183 
 
184 
        subtype mc_opcode       is      std_logic_vector(IN_OP_SIZE     -       1 downto 0);--   size of opcode
185 
 
186 
 
187 
        --      Types   relating        to      the     core
188 
        subtype scratch_addr    is      natural range   0        to      SCRATCH_MEM_SIZE;
189 
 
190 
        type    scratch_mem     is      array(scratch_addr)     of      object;
191 
 
192 
 
193 
        function sign_extend_18_26(bus_18 : std_logic_vector(17 downto 0))return std_logic_vector;
194 
        function mask_flags_match(mask,flags : in std_logic_vector(7 downto 0)) return boolean;
195 
end package;
196 
 
197 
        package body leval_package is
198 
 
199 
        -- Utility
200 
        function sign_extend_18_26(bus_18 : std_logic_vector(17 downto 0))
201 
        return std_logic_vector is
202 
                variable output : std_logic_vector(25 downto 0);
203 
        begin
204 
                output(17 downto 0) := bus_18(17 downto 0);
205 
                output(25 downto 18) := (others => bus_18(17));
206 
                return output;
207 
        end function;
208 
 
209 
        function mask_flags_match(mask, flags : in std_logic_vector(7 downto 0)) return boolean is
210 
        begin
211 
                if (mask(0)  =  flags(0)) or
212 
                        (mask(1)  =  flags(1)) or
213 
                        (mask(2)  =  flags(2)) or
214 
                        (mask(3)  =  flags(3)) or
215 
                        (mask(4)  =  flags(4)) or
216 
                        (mask(5)  =  flags(5)) or
217 
                        (mask(6)  =  flags(6)) or
218 
                        (mask(7)  =  flags(7))
219 
                then
220 
                        return true;
221 
                else
222 
                        return false;
223 
                end if;
224 
        end function;
225 
 
226 
end leval_package;

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