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atypic |
library ieee;
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use ieee.std_logic_1164.all;
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use work.leval_package.all;
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entity toplevel is
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port(
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clk : in std_logic;
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rst_low : in std_logic;
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fpga_data : inout std_logic_vector(WORD_SIZE - 1 downto 0);
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fpga_addr : out std_logic_vector(ADDR_SIZE - 1 downto 0);
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avr_irq : out std_logic;
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avr_rdy : in std_logic;
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sync : in std_logic;
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read : out std_logic;
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write : out std_logic;
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mem_ce : out std_logic_vector(1 downto 0);
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led : out std_logic_vector(7 downto 0);
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err : in std_logic_vector(1 downto 0));
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end entity;
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architecture rtl of toplevel is
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-- Components:
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component leval is
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port (
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rst : in std_logic;
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clk : in std_logic;
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data_in : in std_logic_vector(BUS_SIZE - 1 downto 0);
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data_out : out std_logic_vector(BUS_SIZE - 1 downto 0);
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addr_bus : out std_logic_vector(ADDR_SIZE-1 downto 0);
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wait_s : in std_logic;
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read : out std_logic;
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write : out std_logic;
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sync : in std_logic;
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led : out std_logic_vector(7 downto 0));
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-- DEBUG SIGNALS
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-- pc_out : out std_logic_vector(MC_ADDR_SIZE-1 downto 0);
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-- state_out : out std_logic_vector(3 downto 0);
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-- status_out : out std_logic_vector(STATUS_REG_SIZE-1 downto 0);
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-- pc_write_out : out std_logic);
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end component;
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component addr_decoder is
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port (
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clk : in std_logic;
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leval_addr : in std_logic_vector(ADDR_SIZE - 1 downto 0);
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avr_irq : out std_logic;
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mem_wait : out std_logic;
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mem_ce : out std_logic_vector(1 downto 0);
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read_s : in std_logic;
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write_s : in std_logic);
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end component;
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component synchronizer is
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port (
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clk : in std_logic;
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ws : in std_logic;
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wso : out std_logic);
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end component;
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-- Tristate bus
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component bidirbus is
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port (
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bidir : inout std_logic_vector(WORD_SIZE - 1 downto 0);
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oe : in std_logic;
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clk : in std_logic;
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inp : in std_logic_vector(WORD_SIZE - 1 downto 0);
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outp : out std_logic_vector(WORD_SIZE - 1 downto 0));
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end component;
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-- -- CHIPSCOPE MODULES:
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-- component icon
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-- port (
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-- control0 : out std_logic_vector(35 downto 0);
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-- control1 : out std_logic_vector(35 downto 0));
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-- end component;
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--
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-- component ila
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-- port (
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-- control : in std_logic_vector(35 downto 0);
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-- clk : in std_logic;
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-- trig0 : in std_logic_vector(47 downto 0));
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-- end component;
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--
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-- component vio
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-- port (
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-- control : in std_logic_vector(35 downto 0);
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-- clk : in std_logic;
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-- sync_in : in std_logic_vector(47 downto 0);
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-- sync_out : out std_logic_vector(47 downto 0));
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-- end component;
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--
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-- -- CHIPSCOPE SIGNALS:
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-- signal trig0 : std_logic_vector(47 downto 0);
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-- signal control1 : std_logic_vector(35 downto 0);
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-- signal sync_in : std_logic_vector(47 downto 0);
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-- signal sync_out : std_logic_vector(47 downto 0);
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-- signal control0 : std_logic_vector(35 downto 0);
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-- -- END OF CHIPSCOPE COMPONENTS
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-- -- DEBUG SIGNALS:
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-- signal pc_out : std_logic_vector(MC_ADDR_SIZE-1 downto 0);
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-- signal state_out : std_logic_vector(3 downto 0);
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-- signal pc_write_out : std_logic;
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-- signal status_out : std_logic_vector(STATUS_REG_SIZE-1 downto 0);
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-- signal op1, op2 : std_logic_vector(WORD_SIZE-1 downto 0);
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-- Tristatebus signals
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-- From bidirbus to synchro
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signal t_bus_data_out : std_logic_vector(BUS_SIZE - 1 downto 0);
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-- Synchronizer signals
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-- From synchronizer
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signal sync_ws_out : std_logic;
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-- These give way for flip-flops
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signal read_s_delayed : std_logic;
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signal write_s_delayed : std_logic;
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signal avr_irq_s_delayed : std_logic;
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signal mem_ce_s_delayed : std_logic_vector(1 downto 0);
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signal addr_s_delayed : std_logic_vector(ADDR_SIZE - 1 downto 0);
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-- This is from leval out to the world
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signal leval_data_out : std_logic_vector(BUS_SIZE - 1 downto 0);
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-- Signals:
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signal addr_s : std_logic_vector(ADDR_SIZE - 1 downto 0);
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signal mem_wait_s : std_logic;
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signal mem_wait_and_avr_rdy : std_logic;
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signal write_s : std_logic;
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signal read_s : std_logic;
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signal rst : std_logic;
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signal avr_irq_s : std_logic;
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signal mem_ce_s : std_logic_vector(1 downto 0);
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-- Clock control signals:
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signal leval_clk : std_logic := '0';
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begin
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rst <= not rst_low;
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fpga_addr <= addr_s_delayed;
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read <= not read_s_delayed;
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write <= not write_s_delayed;
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avr_irq <= avr_irq_s_delayed;
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mem_ce <= mem_ce_s_delayed;
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mem_wait_and_avr_rdy <= mem_wait_s and avr_rdy;
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leval_clk <= clk;
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-- -- DEBUG SIGNALS
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-- pc <= pc_out;
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synchronizer_inst : synchronizer
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port map(
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clk => leval_clk,
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ws => mem_wait_and_avr_rdy, --connect the RDY/WAIT signal directly to synchronizer
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wso => sync_ws_out); -- connect the synched RDY/WAIT to leval
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bidirbus_inst : bidirbus
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port map(
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clk => leval_clk,
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oe => write_s,
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bidir => fpga_data,
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inp => leval_data_out, -- from leval into bidirbus
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outp => t_bus_data_out); -- from bidirbus to leval
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leval_inst : leval
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port map(
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clk => leval_clk,
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rst => rst,
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sync => sync,
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data_out => leval_data_out,
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data_in => t_bus_data_out, --connect Tristatebus to data in
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addr_bus => addr_s,
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wait_s => sync_ws_out,
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read => read_s,
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write => write_s,
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led => led);
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-- status_out => status_out,
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-- pc_out => pc_out,
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-- state_out => state_out,
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-- pc_write_out => pc_write_out);
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addr_decoder_inst : addr_decoder
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port map (
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clk => leval_clk,
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leval_addr => addr_s,
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avr_irq => avr_irq_s,
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mem_wait => mem_wait_s,
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mem_ce => mem_ce_s,
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read_s => read_s_delayed,
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write_s => write_s_delayed
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);
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flank_delay : process(clk)
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begin
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if rising_edge(clk) then
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read_s_delayed <= read_s;
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write_s_delayed <= write_s;
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avr_irq_s_delayed <= avr_irq_s;
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mem_ce_s_delayed <= mem_ce_s;
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addr_s_delayed <= addr_s;
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end if;
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end process;
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end architecture rtl;
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