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# Requires: GNU make and basic GNU utilities
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# Xilinx ISE
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#
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# Asbjørn Djupdal 2003, 2008
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###############################################################################
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# IMPORTANT: ucf-file must be named $(PROJECT_NAME).ucf
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###############################################################################
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# the following variables must be set according to your project
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###############################################################################
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ISE_DIR = /opt/Xilinx/11.1/ISE/bin/lin
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# select a name for your project (used as basename for most generated files)
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PROJECT_NAME = leval2
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# list VHDL sourcefiles (separated with spaces) in correct synthesis order
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#SOURCE_FILES = package.vhd bidirbus.vhd synchronizer.vhd alu.vhd addr_decoder.vhd cache.vhdl control.vhd inst_mem.vhd preload_dualport_mem.vhd singleport_mem.vhd if.vhd id.vhd ex.vhd mem.vhd whisk.vhd
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SOURCE_FILES = pipelineregs.vhd leval2_constants.vhd forward.vhd hazard.vhd rrwmem.vhd rwmem.vhd alu.vhd control.vhd addr_decoder.vhd bidirbus.vhd toplevel.vhd leval2.vhd
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# name of top level entity
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TOP_LEVEL = toplevel
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# target device
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DEVICE = XC3S500E-5-pq208
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# synthesis (xst) options
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SYNTH_OPTS = -opt_mode Speed -opt_level 1 -register_duplication no \
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-hierarchy_separator / -keep_hierarchy yes -uc toplevel.xcf
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# options for bitfile generation
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BITGEN_OPTS = -g DriveDone:No -g StartUpClk:JTAGCLK \
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-g DONE_cycle:4 -g GTS_cycle:5 -g DonePipe:No \
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-g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:NONE
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###############################################################################
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# rules, no need to change anything below this line
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###############################################################################
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# default rule: create both bitfile and files for timing simulation
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.PHONY : default
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default : $(PROJECT_NAME).bit time_sim.vhd
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# create temporary project and script files for XST
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$(PROJECT_NAME).xst : $(SOURCE_FILES)
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exec /opt/Xilinx/11.1/ISE/settings32.sh
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echo $(SOURCE_FILES) | xargs -n 1 > $(PROJECT_NAME).prj
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echo -n "run -ifn $(PROJECT_NAME).prj -ofn $(PROJECT_NAME).ngc " > $@
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echo -n "-ofmt NGC -p $(DEVICE) -top $(TOP_LEVEL) -ifmt VHDL " >> $@
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echo "$(SYNTH_OPTS)" >> $@
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# synthesis with XST
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$(PROJECT_NAME).ngc : $(PROJECT_NAME).xst
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$(ISE_DIR)/xst -ifn $<
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# implementation
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$(PROJECT_NAME).ncd : $(PROJECT_NAME).ngc
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$(ISE_DIR)/xflow -p $(DEVICE) -implement high_effort.opt $<
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# bitfile generation
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$(PROJECT_NAME).bit : $(PROJECT_NAME).ncd $(PROJECT_NAME).pcf
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$(ISE_DIR)/bitgen -l -w -m -intstyle xflow $(BITGEN_OPTS) $<
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# generate files for timing simulation
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time_sim.vhd : $(PROJECT_NAME).ncd $(PROJECT_NAME).pcf
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$(ISE_DIR)/xflow -p $(DEVICE) -tsim modelsim_vhdl.opt $<
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.PHONY : clean
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clean :
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rm -rf *.opt *.flw *.bgn *.bit *.bld *.drc *.ll *.msk *.ncd *.ngc \
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*.ngd *.pad *.par *.pcf *.prj *.rbt *.twr *.twx *.xpi *_map* \
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*_pad* *_timing* *_xst* *.lst *.nlf *.sdf xflow* xst *.xst \
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*.srp .prj .srp .xst
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