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atypic |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.leval2_pipelineregs.all;
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use work.leval2_package.all;
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entity leval2 is
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port (
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clk : in std_logic;
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rst : in std_logic;
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data_in : in std_logic_vector (BUS_BITS - 1 downto 0);
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data_out : in std_logic_vector (BUS_BITS - 1 downto 0);
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addr_bus : out std_logic_vector (ADDR_BITS - 1 downto 0);
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iowait : in std_logic;
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Sync : in std_logic;
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read : out std_logic;
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write : out std_logic;
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led : out std_logic_vector(7 downto 0));
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end entity;
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architecture mixed of leval2 is
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----------------------------------------------------
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-- Pipeline register instances.
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----------------------------------------------------
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signal IFID : IFID_t;
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signal IDEX : IDEX_t;
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signal EXMEM : EXMEM_t;
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signal M1M2 : M1M2_t;
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signal M2WB : M2WB_t;
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----------------------------------------------------
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-- Signals from/internal to stages
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----------------------------------------------------
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-- Fetch
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----------------------------------------------------------------------------
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signal PC : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
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signal PCincremented : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
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-- signal PCmuxin : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
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signal InstrMemWe : std_logic;
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signal InstrWriteData : std_logic_vector(MC_INSTR_BITS - 1 downto 0);
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signal InstrWriteAddress : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
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signal Instruction : std_logic_vector(MC_INSTR_BITS - 1 downto 0);
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-- Signals from decode stage
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----------------------------------------------------------------------------
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signal RegAddr1 : std_logic_vector(REGS_ADDR_BITS - 1 downto 0);
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signal RegAddr2 : std_logic_vector(REGS_ADDR_BITS - 1 downto 0);
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signal RegData1 : std_logic_vector(WORD_BITS - 1 downto 0);
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signal RegData2 : std_logic_vector(WORD_BITS - 1 downto 0);
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signal IndirReg1Sel : std_logic;
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signal IndirReg2Sel : std_logic;
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-- Signals from execute stage
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----------------------------------------------------------------------------
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signal Flags : std_logic_vector(STATUS_REG_BITS - 1 downto 0);
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signal AluRes : std_logic_vector(OBJECT_SIZE - 1 downto 0);
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signal AluIn1 : std_logic_vector(OBJECT_SIZe - 1 downto 0);
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signal AluIn2 : std_logic_vector(OBJECT_SIZe - 1 downto 0);
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-- Signals from/internal to memory 1 stage
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----------------------------------------------------------------------------
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signal Tag : std_logic_vector(CACHE_TAG_BITS - 1 downto 0);
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signal BranchTaken : std_logic;
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-- Signals from memory 2 stage
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----------------------------------------------------------------------------
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signal CacheHit : std_logic;
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signal WriteCache : std_logic;
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signal MemSrc : std_logic_vector(WORD_BITS - 1 downto 0);
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signal CachedData : std_logic_vector(WORD_BITS - 1 downto 0);
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-- Signals from write-back stage
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----------------------------------------------------------------------------
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signal WriteData : std_logic_vector(WORD_BITS - 1 downto 0);
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-- Signals from control
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----------------------------------------------------------------------------
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signal PCMuxSel : std_logic_vector(1 downto 0);
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signal AluOp : std_logic_vector(ALU_FUNCT_SIZE - 1 downto 0);
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signal WriteReg : std_logic;
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signal MemToReg : std_logic;
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signal Store : std_logic;
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signal AluIn2Src : std_logic;
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signal IndirMux1 : std_logic;
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signal IndirMux2 : std_logic;
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signal Flush : std_logic;
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signal Branch : std_logic;
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signal Stall : std_logic;
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-- Signals from forward
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signal FwdMux1 : std_logic_vector(2 downto 0);
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signal FwdMux2 : std_logic_vector(2 downto 0);
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-- Signals from hazard
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----------------------------------------------------------------------------
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signal Hazard : std_logic;
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-- Signals from outside
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----------------------------------------------------------------------------
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signal LoadedMem : std_logic_vector(WORD_BITS - 1 downto 0);
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signal WritingMem : std_logic_vector(WORD_BITS - 1 downto 0);
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-- signal Sync : std_logic;
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signal MemWait : std_logic;
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begin
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----------------------------------------------------
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-- Control unit
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----------------------------------------------------
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control_unit : entity control
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port map (
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IndirReg1Sel,
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IndirReg2Sel,
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PCMuxSel,
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AluOp,
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WriteReg,
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Flush,
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MemToReg,
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IndirMux1,
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IndirMux2,
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Branch,
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Store,
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Stall,
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Instruction(INSTR_OPCODE_START downto INSTR_OPCODE_END),
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MemWait,
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Sync,
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BranchTaken,
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Hazard
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);
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----------------------------------------------------
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-- Forwarding unit
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----------------------------------------------------
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forwarding_unit : entity Forward
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port map (
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IDEX.AluIn2Src,
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IDEX.Branch,
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IDEX.IR(INSTR_REG1_START downto INSTR_REG1_END),
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IDEX.IR(INSTR_REG2_START downto INSTR_REG2_END),
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EXMEM.IR(INSTR_REG1_START downto INSTR_REG1_END),
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EXMEM.IR(INSTR_REG2_START downto INSTR_REG2_END),
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M2WB.IR(INSTR_REG1_START downto INSTR_REG1_END),
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M2WB.IR(INSTR_REG2_START downto INSTR_REG2_END),
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FwdMux1,
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FwdMux2
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);
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----------------------------------------------------
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-- Hazard unit
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----------------------------------------------------
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hazard_detection : entity Hazard
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port map (
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Instruction(INSTR_OPCODE_START downto INSTR_OPCODE_END),
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Instruction(INSTR_REG1_START downto INSTR_REG1_END),
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Instruction(INSTR_REG2_START downto INSTR_REG2_END),
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IDEX.IR(INSTR_OPCODE_START downto INSTR_OPCODE_END),
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IDEX.IR(INSTR_REG1_START downto INSTR_REG1_END),
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IDEX.IR(INSTR_REG2_START downto INSTR_REG2_END),
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EXMEM.IR(INSTR_OPCODE_START downto INSTR_OPCODE_END),
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EXMEM.IR(INSTR_REG1_START downto INSTR_REG1_END),
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EXMEM.IR(INSTR_REG2_START downto INSTR_REG2_END),
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Hazard );
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----------------------------------------------------
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-- Fetch stage
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----------------------------------------------------
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PCincremented <= std_logic_vector(unsigned(PC) + 1);
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instr_mem : entity rwmem
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generic map (
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INSTR_MEM_SIZE,
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MC_ADDR_BITS,
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MC_INSTR_BITS)
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port map (
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clk,
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InstrMemWe,
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PC,
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InstrWriteAddress,
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InstrWriteData,
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Instruction);
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instr_fetch : process (clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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PC <= (others => '0');
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elsif PCMuxSel = "00" then -- pipeline stall
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PC <= PC;
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IFID.PC <= PC;
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elsif PCMUxSel = "01" then
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PC <= EXMEM.AluRes(MC_ADDR_BITS - 1 downto 0);
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IFID.PC <= EXMEM.AluRes(MC_ADDR_BITS - 1 downto 0);
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else
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PC <= PCIncremented;
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IFID.PC <= PCIncremented;
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end if;
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if Flush = '1' then
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IFID.PC <= (others => '0');
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end if;
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end if;
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end process;
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----------------------------------------------------
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-- Decode stage
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----------------------------------------------------
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-- If we stored the indirect-bits in the previous cycle,
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-- we now shall use the results from that register fetch
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-- to address the new fetch, but avoid looping by anding with negated.
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IndirReg1Sel <= not IDEX.IndirReg1bit and Instruction(INSTR_REG1_INDIR);
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IndirReg2Sel <= not IDEX.IndirReg2bit and Instruction(INSTR_REG2_INDIR);
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-- Indirection multiplexers
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RegAddr1 <= Instruction(INSTR_REG1_START downto INSTR_REG1_END)
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when IndirMux1 = '0'
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else IDEX.IndirReg1;
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RegAddr2 <= Instruction(INSTR_REG2_START downto INSTR_REG2_END)
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when IndirMux2 = '0'
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else IDEX.IndirReg2;
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regfile : entity rrwmem
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generic map (
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memsize => REGS_SIZE,
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addr_width => REGS_ADDR_BITS,
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data_width => WORD_BITS,
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initfile => SCRATCH_MEM_INIT)
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port map (
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clk,
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M2WB.WriteReg,
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RegAddr1,
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RegAddr2,
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M2WB.IR(INSTR_REG1_START downto INSTR_REG1_END),
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WriteData,
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RegData1,
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RegData2);
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instr_decode : process (clk)
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begin
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if rising_edge(clk) then
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IDEX.WriteReg <= WriteReg;
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IDEX.MemToReg <= MemToReg;
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IDEX.Store <= Store;
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IDEX.AluIn2Src <= AluIn2Src;
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IDEX.AluOp <= AluOp;
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IDEX.IndirReg1bit <= Instruction(INSTR_REG1_INDIR);
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IDEX.IndirReg2bit <= Instruction(INSTR_REG2_INDIR);
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IDEX.Branch <= Branch;
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IDEX.IR <= Instruction;
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IDEX.PC <= IFID.PC;
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IDEX.Immediate <= sign_extend_18_26(Instruction(INSTR_IMM_START downto 0));
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-- Flushing and stalling control paths.
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if Flush = '1' then
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IDEX.WriteReg <= '0';
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IDEX.MemToReg <= '0';
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IDEX.Store <= '0';
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IDEX.AluIn2Src <= '0';
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IDEX.AluOp <= ALU_PASS;
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IDEX.IndirReg1bit <= '0';
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IDEX.IndirReg2bit <= '0';
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IDEX.Branch <= '0';
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IDEX.IR <= (others=>'0');
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IDEX.PC <= (others=>'0');
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IDEX.Immediate <= (others=>'0');
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elsif Stall = '1' then
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IDEX.WriteReg <= IDEX.WriteReg;
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IDEX.MemToReg <= IDEX.MemToReg;
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IDEX.Store <= IDEX.Store;
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IDEX.AluIn2Src <= IDEX.AluIn2Src;
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IDEX.AluOp <= IDEX.AluOp;
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IDEX.IndirReg1bit <= IDEX.IndirReg1bit;
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IDEX.IndirReg2bit <= IDEX.IndirReg2bit;
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IDEX.Branch <= IDEX.Branch;
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IDEX.IR <= IDEX.IR;
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IDEX.PC <= IDEX.PC;
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IDEX.Immediate <= IDEX.Immediate;
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end if;
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end if;
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end process;
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----------------------------------------------------
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-- Execution stage
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----------------------------------------------------
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-- Forwarding muxes
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fwd_mux1 : process (FwdMux1, RegData1, IDEX.PC, M2WB.MemWriteData, M2WB.AluRes, EXMEM.AluRes)
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begin
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case FwdMux1 is
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when FWD_BRANCH =>
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AluIn1 <= IDEX.PC;
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when FWD_REGDATA =>
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AluIn1 <= RegData1;
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when FWD_1_EXMEM_ALURES =>
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AluIn1 <= EXMEM.AluRes;
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when FWD_1_M2WB_ALURES =>
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AluIn1 <= M2WB.AluRes;
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when FWD_1_M2WB_MEMWRITEDATA =>
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AluIn1 <= M2WB.MemWriteData;
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when others =>
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AluIn1 <= "00000000000000000000000000000000";
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end case;
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end process;
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fwd_mux2 : process (FwdMux2, RegData2, IDEX.Immediate, M2WB.MemWriteData, M2WB.AluRes, EXMEM.AluRes)
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begin
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326 |
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case FwdMux2 is
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when FWD_2_IMMEDIATE =>
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AluIn2 <= IDEX.Immediate;
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when FWD_REGDATA =>
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AluIn2 <= RegData2;
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when FWD_2_EXMEM_ALURES =>
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AluIn2 <= EXMEM.AluRes;
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when FWD_2_M2WB_ALURES =>
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AluIn2 <= M2WB.AluRes;
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when FWD_2_M2WB_MEMWRITEDATA =>
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AluIn2 <= M2WB.MemWriteData;
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when others =>
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AluIn2 <= "00000000000000000000000000000000";
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end case;
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end process;
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341 |
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342 |
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343 |
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344 |
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main_alu : entity alu
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345 |
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port map (
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346 |
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AluIn1,
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347 |
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AluIn2,
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348 |
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IDEX.AluOp,
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349 |
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Flags,
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AluRes
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);
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352 |
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exec_stage : process (clk)
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353 |
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begin
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354 |
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if rising_edge(clk) then
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EXMEM.WriteReg <= IDEX.WriteReg;
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356 |
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EXMEM.MemToReg <= IDEX.MemToReg;
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357 |
|
|
EXMEM.Store <= IDEX.Store;
|
358 |
|
|
EXMEM.IR <= IDEX.IR;
|
359 |
|
|
EXMEM.AluRes <= AluRes;
|
360 |
|
|
EXMEM.MemWriteData <= RegData2;
|
361 |
|
|
end if;
|
362 |
|
|
end process;
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
----------------------------------------------------
|
367 |
|
|
-- Memory stage 1
|
368 |
|
|
----------------------------------------------------
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
tags : entity rwmem
|
372 |
|
|
generic map (
|
373 |
|
|
CACHE_LINES,
|
374 |
|
|
CACHE_INDEX_BITS,
|
375 |
|
|
CACHE_TAG_BITS)
|
376 |
|
|
|
377 |
|
|
port map (
|
378 |
|
|
clk,
|
379 |
|
|
WriteCache,
|
380 |
|
|
EXMEM.AluRes(CACHE_INDEX_POS downto 0),
|
381 |
|
|
M1M2.Address(CACHE_INDEX_POS downto 0) ,--write addr
|
382 |
|
|
M1M2.Tag,--write data
|
383 |
|
|
Tag);
|
384 |
|
|
|
385 |
|
|
|
386 |
|
|
data : entity rwmem
|
387 |
|
|
generic map (
|
388 |
|
|
CACHE_LINES,
|
389 |
|
|
CACHE_INDEX_BITS,
|
390 |
|
|
CACHE_DATA_BITS)
|
391 |
|
|
|
392 |
|
|
port map (
|
393 |
|
|
clk,
|
394 |
|
|
WriteCache,
|
395 |
|
|
EXMEM.AluRes(CACHE_INDEX_POS downto 0),
|
396 |
|
|
M1M2.Address(CACHE_INDEX_POS downto 0) ,--write addr
|
397 |
|
|
MemSrc,--write data
|
398 |
|
|
CachedData);
|
399 |
|
|
|
400 |
|
|
mem1 : process (clk)
|
401 |
|
|
begin
|
402 |
|
|
if rising_edge(clk) then
|
403 |
|
|
M1M2.WriteReg <= EXMEM.WriteReg;
|
404 |
|
|
M1M2.MemToReg <= EXMEM.MemToReg;
|
405 |
|
|
M1M2.Store <= EXMEM.Store;
|
406 |
|
|
|
407 |
|
|
M1M2.IR <= EXMEM.IR;
|
408 |
|
|
M1M2.Tag <= Tag;
|
409 |
|
|
M1M2.Address <= EXMEM.AluRes;
|
410 |
|
|
M1M2.Data <= CachedData;
|
411 |
|
|
M1M2.MemWriteData <= EXMEM.MemWriteData;
|
412 |
|
|
|
413 |
|
|
if Stall = '1' then
|
414 |
|
|
M1M2.WriteReg <= M1M2.WriteReg ;
|
415 |
|
|
M1M2.MemToReg <= M1M2.MemToReg ;
|
416 |
|
|
M1M2.Store <= M1M2.Store ;
|
417 |
|
|
|
418 |
|
|
M1M2.IR <= M1M2.IR ;
|
419 |
|
|
M1M2.Tag <= M1M2.Tag ;
|
420 |
|
|
M1M2.Address <= M1M2.Address ;
|
421 |
|
|
M1M2.Data <= M1M2.Data ;
|
422 |
|
|
M1M2.MemWriteData <= M1M2.MemWriteData ;
|
423 |
|
|
end if;
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
end if;
|
427 |
|
|
end process;
|
428 |
|
|
|
429 |
|
|
----------------------------------------------------
|
430 |
|
|
-- Memory stage 2
|
431 |
|
|
----------------------------------------------------
|
432 |
|
|
|
433 |
|
|
addr_bus <= M1M2.Address;
|
434 |
|
|
|
435 |
|
|
-- Tag compare
|
436 |
|
|
CacheHit <= '1' when M1M2.Tag = M1M2.Address(CACHE_TAG_START downto CACHE_TAG_END);
|
437 |
|
|
WriteCache <= not CacheHit;
|
438 |
|
|
|
439 |
|
|
LoadedMem <= data_in;
|
440 |
|
|
WritingMem <= data_out;
|
441 |
|
|
|
442 |
|
|
MemWait <= iowait; -- From outside.
|
443 |
|
|
|
444 |
|
|
-- The cache result mux
|
445 |
|
|
memmux : process(M1M2.Data, M1M2.MemWriteData, LoadedMem)
|
446 |
|
|
begin
|
447 |
|
|
if M1M2.Store = '1' then
|
448 |
|
|
MemSrc <= M1M2.Data; -- don't care: we're storing.
|
449 |
|
|
elsif M1M2.Store = '0' and CacheHit = '1' then -- cache hit
|
450 |
|
|
MemSrc <= M1M2.Data;
|
451 |
|
|
elsif MemToReg = '1' and CacheHit = '0' then -- cache miss
|
452 |
|
|
MemSrc <= LoadedMem;
|
453 |
|
|
end if;
|
454 |
|
|
end process;
|
455 |
|
|
|
456 |
|
|
|
457 |
|
|
|
458 |
|
|
mem2 : process (clk)
|
459 |
|
|
begin
|
460 |
|
|
|
461 |
|
|
write <= M1M2.Store; -- to outside
|
462 |
|
|
read <= '0';
|
463 |
|
|
|
464 |
|
|
if rising_edge(clk) then
|
465 |
|
|
M2WB.WriteReg <= M1M2.WriteReg;
|
466 |
|
|
M2WB.MemToReg <= M1M2.MemToReg;
|
467 |
|
|
|
468 |
|
|
M2WB.IR <= M1M2.IR;
|
469 |
|
|
M2WB.AluRes <= M1M2.Address;
|
470 |
|
|
M2WB.MemWriteData <= MemSrc;
|
471 |
|
|
|
472 |
|
|
if Stall = '1' then
|
473 |
|
|
M2WB.WriteReg <= M2WB.WriteReg ;
|
474 |
|
|
M2WB.MemToReg <= M2WB.MemToReg ;
|
475 |
|
|
M2WB.IR <= M2WB.IR ;
|
476 |
|
|
M2WB.AluRes <= M2WB.AluRes ;
|
477 |
|
|
M2WB.MemWriteData <= M2WB.MemWriteData ;
|
478 |
|
|
end if;
|
479 |
|
|
end if;
|
480 |
|
|
end process;
|
481 |
|
|
|
482 |
|
|
----------------------------------------------------
|
483 |
|
|
-- Write back
|
484 |
|
|
----------------------------------------------------
|
485 |
|
|
WriteData <= M2WB.AluRes when M2WB.MemToReg = '0' else M2WB.MemWriteData;
|
486 |
|
|
|
487 |
|
|
end architecture;
|