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[/] [igor/] [trunk/] [processor/] [pl/] [leval2.vhd] - Blame information for rev 4

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
use work.leval2_pipelineregs.all;
use work.leval2_package.all;
 
entity leval2 is
    port (
    clk : in std_logic;
    rst : in std_logic;
    data_in : in std_logic_vector (BUS_BITS - 1 downto 0);
    data_out : in std_logic_vector (BUS_BITS - 1 downto 0);
    addr_bus : out std_logic_vector (ADDR_BITS - 1 downto 0);
    iowait : in std_logic;
    Sync : in std_logic;
    read : out std_logic;
    write : out std_logic;
    led : out std_logic_vector(7 downto 0));
end entity;
 
 
architecture mixed of leval2 is
    ----------------------------------------------------
    -- Pipeline register instances.
    ----------------------------------------------------
    signal IFID : IFID_t;
    signal IDEX : IDEX_t;
    signal EXMEM : EXMEM_t;
    signal M1M2 : M1M2_t;
    signal M2WB : M2WB_t;
 
 
        ----------------------------------------------------
    -- Signals from/internal to stages
    ----------------------------------------------------
 
    -- Fetch
    ----------------------------------------------------------------------------
    signal PC : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
    signal PCincremented : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
--    signal PCmuxin : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
        signal InstrMemWe : std_logic;
        signal InstrWriteData : std_logic_vector(MC_INSTR_BITS - 1 downto 0);
        signal InstrWriteAddress : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
        signal Instruction : std_logic_vector(MC_INSTR_BITS - 1 downto 0);
 
    -- Signals from decode stage
    ----------------------------------------------------------------------------
        signal RegAddr1 : std_logic_vector(REGS_ADDR_BITS - 1 downto 0);
        signal RegAddr2 : std_logic_vector(REGS_ADDR_BITS - 1 downto 0);
    signal RegData1 : std_logic_vector(WORD_BITS - 1 downto 0);
    signal RegData2 : std_logic_vector(WORD_BITS - 1 downto 0);
    signal IndirReg1Sel : std_logic;
    signal IndirReg2Sel : std_logic;
 
    -- Signals from execute stage
    ----------------------------------------------------------------------------
    signal Flags : std_logic_vector(STATUS_REG_BITS - 1 downto 0);
    signal AluRes : std_logic_vector(OBJECT_SIZE - 1 downto 0);
    signal AluIn1 : std_logic_vector(OBJECT_SIZe - 1 downto 0);
    signal AluIn2 : std_logic_vector(OBJECT_SIZe - 1 downto 0);
 
 
    -- Signals from/internal to memory 1 stage
    ----------------------------------------------------------------------------
        signal Tag : std_logic_vector(CACHE_TAG_BITS - 1 downto 0);
    signal BranchTaken : std_logic;
 
    -- Signals from memory 2 stage
    ----------------------------------------------------------------------------
        signal CacheHit : std_logic;
        signal WriteCache : std_logic;
        signal MemSrc : std_logic_vector(WORD_BITS - 1 downto 0);
        signal CachedData : std_logic_vector(WORD_BITS - 1 downto 0);
 
    -- Signals from write-back stage
    ----------------------------------------------------------------------------
    signal WriteData : std_logic_vector(WORD_BITS - 1 downto 0);
 
    -- Signals from control
    ----------------------------------------------------------------------------
    signal PCMuxSel : std_logic_vector(1 downto 0);
    signal AluOp : std_logic_vector(ALU_FUNCT_SIZE - 1 downto 0);
    signal WriteReg : std_logic;
    signal MemToReg : std_logic;
    signal Store : std_logic;
    signal AluIn2Src : std_logic;
    signal IndirMux1 : std_logic;
    signal IndirMux2 : std_logic;
    signal Flush : std_logic;
        signal Branch : std_logic;
    signal Stall : std_logic;
 
 
    -- Signals from forward
    signal FwdMux1 : std_logic_vector(2 downto 0);
    signal FwdMux2 : std_logic_vector(2 downto 0);
 
    -- Signals from hazard
    ----------------------------------------------------------------------------
        signal Hazard : std_logic;
 
        -- Signals from outside
    ----------------------------------------------------------------------------
        signal LoadedMem : std_logic_vector(WORD_BITS - 1 downto 0);
        signal WritingMem : std_logic_vector(WORD_BITS - 1 downto 0);
--      signal Sync : std_logic;
    signal MemWait : std_logic;
 
 
 
begin
    ----------------------------------------------------
    -- Control unit
    ----------------------------------------------------
    control_unit : entity control
    port map (
        IndirReg1Sel,
        IndirReg2Sel,
        PCMuxSel,
        AluOp,
        WriteReg,
        Flush,
        MemToReg,
        IndirMux1,
        IndirMux2,
                Branch,
                Store,
        Stall,
        Instruction(INSTR_OPCODE_START downto INSTR_OPCODE_END),
        MemWait,
                Sync,
        BranchTaken,
                Hazard
             );
 
        ----------------------------------------------------
        -- Forwarding unit
    ----------------------------------------------------
        forwarding_unit : entity Forward
        port map (
                IDEX.AluIn2Src,
                IDEX.Branch,
                IDEX.IR(INSTR_REG1_START downto INSTR_REG1_END),
                IDEX.IR(INSTR_REG2_START downto INSTR_REG2_END),
                EXMEM.IR(INSTR_REG1_START downto INSTR_REG1_END),
                EXMEM.IR(INSTR_REG2_START downto INSTR_REG2_END),
                M2WB.IR(INSTR_REG1_START downto INSTR_REG1_END),
                M2WB.IR(INSTR_REG2_START downto INSTR_REG2_END),
                FwdMux1,
                FwdMux2
        );
 
        ----------------------------------------------------
        -- Hazard unit
    ----------------------------------------------------
        hazard_detection : entity Hazard
        port map (
        Instruction(INSTR_OPCODE_START downto INSTR_OPCODE_END),
                Instruction(INSTR_REG1_START downto INSTR_REG1_END),
                Instruction(INSTR_REG2_START downto INSTR_REG2_END),
                IDEX.IR(INSTR_OPCODE_START downto INSTR_OPCODE_END),
                IDEX.IR(INSTR_REG1_START downto INSTR_REG1_END),
                IDEX.IR(INSTR_REG2_START downto INSTR_REG2_END),
                EXMEM.IR(INSTR_OPCODE_START downto INSTR_OPCODE_END),
                EXMEM.IR(INSTR_REG1_START downto INSTR_REG1_END),
                EXMEM.IR(INSTR_REG2_START downto INSTR_REG2_END),
                Hazard );
 
 
 
 
 
    ----------------------------------------------------
    -- Fetch stage
    ----------------------------------------------------
    PCincremented <= std_logic_vector(unsigned(PC) + 1);
 
        instr_mem : entity rwmem
        generic map (
                INSTR_MEM_SIZE,
                MC_ADDR_BITS,
                MC_INSTR_BITS)
 
        port map (
                clk,
                InstrMemWe,
                PC,
                InstrWriteAddress,
                InstrWriteData,
                Instruction);
 
    instr_fetch : process (clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                PC <= (others => '0');
            elsif PCMuxSel = "00" then -- pipeline stall
                PC <= PC;
                                IFID.PC <= PC;
            elsif PCMUxSel = "01" then
                PC <= EXMEM.AluRes(MC_ADDR_BITS - 1 downto 0);
                                IFID.PC <= EXMEM.AluRes(MC_ADDR_BITS - 1 downto 0);
            else
                PC <= PCIncremented;
                                IFID.PC <= PCIncremented;
            end if;
 
            if Flush = '1' then
                IFID.PC <= (others => '0');
            end if;
 
        end if;
    end process;
 
 
    ----------------------------------------------------
    -- Decode stage
    ----------------------------------------------------
 
    -- If we stored the indirect-bits in the previous cycle,
    -- we now shall use the results from that register fetch
    -- to address the new fetch, but avoid looping by anding with negated.
    IndirReg1Sel <= not IDEX.IndirReg1bit and Instruction(INSTR_REG1_INDIR);
    IndirReg2Sel <= not IDEX.IndirReg2bit and Instruction(INSTR_REG2_INDIR);
 
 
        -- Indirection multiplexers
        RegAddr1 <= Instruction(INSTR_REG1_START downto INSTR_REG1_END)
                                when IndirMux1 = '0'
                                else IDEX.IndirReg1;
 
        RegAddr2 <= Instruction(INSTR_REG2_START downto INSTR_REG2_END)
                                when IndirMux2 = '0'
                                else IDEX.IndirReg2;
 
    regfile : entity rrwmem
    generic map (
        memsize => REGS_SIZE,
        addr_width => REGS_ADDR_BITS,
        data_width => WORD_BITS,
        initfile => SCRATCH_MEM_INIT)
    port map (
        clk,
        M2WB.WriteReg,
                RegAddr1,
                RegAddr2,
                M2WB.IR(INSTR_REG1_START downto INSTR_REG1_END),
        WriteData,
        RegData1,
        RegData2);
 
    instr_decode : process (clk)
    begin
        if rising_edge(clk) then
            IDEX.WriteReg <= WriteReg;
            IDEX.MemToReg <= MemToReg;
            IDEX.Store <= Store;
            IDEX.AluIn2Src <= AluIn2Src;
            IDEX.AluOp <= AluOp;
            IDEX.IndirReg1bit <= Instruction(INSTR_REG1_INDIR);
            IDEX.IndirReg2bit <= Instruction(INSTR_REG2_INDIR);
            IDEX.Branch <= Branch;
            IDEX.IR <= Instruction;
            IDEX.PC <= IFID.PC;
            IDEX.Immediate <= sign_extend_18_26(Instruction(INSTR_IMM_START downto 0));
 
            -- Flushing and stalling control paths. 
            if Flush = '1' then
                IDEX.WriteReg <= '0';
                IDEX.MemToReg <= '0';
                IDEX.Store <= '0';
                IDEX.AluIn2Src <= '0';
                IDEX.AluOp <= ALU_PASS;
                IDEX.IndirReg1bit <= '0';
                IDEX.IndirReg2bit <= '0';
                IDEX.Branch <= '0';
                IDEX.IR <= (others=>'0');
                IDEX.PC <= (others=>'0');
                IDEX.Immediate <= (others=>'0');
            elsif Stall = '1' then
                IDEX.WriteReg <= IDEX.WriteReg;
                IDEX.MemToReg <= IDEX.MemToReg;
                IDEX.Store <= IDEX.Store;
                IDEX.AluIn2Src <= IDEX.AluIn2Src;
                IDEX.AluOp <= IDEX.AluOp;
                IDEX.IndirReg1bit <= IDEX.IndirReg1bit;
                IDEX.IndirReg2bit <= IDEX.IndirReg2bit;
                IDEX.Branch <= IDEX.Branch;
                IDEX.IR <= IDEX.IR;
                IDEX.PC <= IDEX.PC;
                IDEX.Immediate <= IDEX.Immediate;
            end if;
        end if;
    end process;
 
 
 
    ----------------------------------------------------
    -- Execution stage
    ----------------------------------------------------
    -- Forwarding muxes
 
    fwd_mux1 : process (FwdMux1, RegData1, IDEX.PC, M2WB.MemWriteData, M2WB.AluRes, EXMEM.AluRes)
    begin
        case FwdMux1 is
            when FWD_BRANCH =>
                AluIn1 <= IDEX.PC;
            when FWD_REGDATA =>
                AluIn1 <= RegData1;
            when FWD_1_EXMEM_ALURES =>
                AluIn1 <= EXMEM.AluRes;
            when FWD_1_M2WB_ALURES =>
                AluIn1 <= M2WB.AluRes;
            when FWD_1_M2WB_MEMWRITEDATA =>
                AluIn1 <= M2WB.MemWriteData;
                        when others =>
                                AluIn1 <= "00000000000000000000000000000000";
        end case;
        end process;
 
        fwd_mux2 : process (FwdMux2, RegData2, IDEX.Immediate, M2WB.MemWriteData, M2WB.AluRes, EXMEM.AluRes)
    begin
        case FwdMux2 is
            when FWD_2_IMMEDIATE =>
                AluIn2 <= IDEX.Immediate;
            when FWD_REGDATA =>
                AluIn2 <= RegData2;
            when FWD_2_EXMEM_ALURES =>
                AluIn2 <= EXMEM.AluRes;
            when FWD_2_M2WB_ALURES =>
                AluIn2 <= M2WB.AluRes;
            when FWD_2_M2WB_MEMWRITEDATA =>
                AluIn2 <= M2WB.MemWriteData;
                        when others =>
                                AluIn2 <= "00000000000000000000000000000000";
        end case;
        end process;
 
 
 
    main_alu : entity alu
    port map (
        AluIn1,
        AluIn2,
        IDEX.AluOp,
        Flags,
        AluRes
             );
    exec_stage : process (clk)
    begin
        if rising_edge(clk) then
            EXMEM.WriteReg <= IDEX.WriteReg;
            EXMEM.MemToReg <= IDEX.MemToReg;
            EXMEM.Store <= IDEX.Store;
            EXMEM.IR <= IDEX.IR;
            EXMEM.AluRes <= AluRes;
            EXMEM.MemWriteData <= RegData2;
        end if;
    end process;
 
 
 
    ----------------------------------------------------
    -- Memory stage 1
    ----------------------------------------------------
 
 
        tags : entity rwmem
        generic map (
                CACHE_LINES,
                CACHE_INDEX_BITS,
                CACHE_TAG_BITS)
 
        port map (
                clk,
                WriteCache,
                EXMEM.AluRes(CACHE_INDEX_POS downto 0),
                M1M2.Address(CACHE_INDEX_POS downto 0) ,--write addr
                M1M2.Tag,--write data
                Tag);
 
 
        data : entity rwmem
        generic map (
                CACHE_LINES,
                CACHE_INDEX_BITS,
                CACHE_DATA_BITS)
 
        port map (
                clk,
                WriteCache,
                EXMEM.AluRes(CACHE_INDEX_POS downto 0),
                M1M2.Address(CACHE_INDEX_POS downto 0) ,--write addr
                MemSrc,--write data
                CachedData);
 
        mem1 : process (clk)
        begin
                if rising_edge(clk) then
                        M1M2.WriteReg <= EXMEM.WriteReg;
                        M1M2.MemToReg <= EXMEM.MemToReg;
                        M1M2.Store <= EXMEM.Store;
 
                        M1M2.IR <= EXMEM.IR;
                        M1M2.Tag <= Tag;
                        M1M2.Address <= EXMEM.AluRes;
                        M1M2.Data <= CachedData;
                        M1M2.MemWriteData <= EXMEM.MemWriteData;
 
            if Stall = '1' then
                 M1M2.WriteReg  <=  M1M2.WriteReg ;
                 M1M2.MemToReg  <=  M1M2.MemToReg ;
                 M1M2.Store  <=  M1M2.Store ;
 
                 M1M2.IR  <=  M1M2.IR ;
                 M1M2.Tag  <=  M1M2.Tag ;
                 M1M2.Address  <=  M1M2.Address ;
                 M1M2.Data  <=  M1M2.Data ;
                 M1M2.MemWriteData  <=  M1M2.MemWriteData ;
            end if;
 
 
                end if;
        end process;
 
        ----------------------------------------------------
    -- Memory stage 2
    ----------------------------------------------------
 
        addr_bus <= M1M2.Address;
 
        -- Tag compare
        CacheHit <= '1' when M1M2.Tag = M1M2.Address(CACHE_TAG_START downto CACHE_TAG_END);
        WriteCache <= not CacheHit;
 
        LoadedMem <= data_in;
        WritingMem <= data_out;
 
        MemWait <= iowait; -- From outside.
 
        -- The cache result mux
        memmux : process(M1M2.Data, M1M2.MemWriteData, LoadedMem)
        begin
                if M1M2.Store = '1' then
                        MemSrc <= M1M2.Data; -- don't care: we're storing.
                elsif M1M2.Store = '0' and CacheHit = '1' then -- cache hit
                        MemSrc <= M1M2.Data;
                elsif MemToReg = '1' and CacheHit = '0' then -- cache miss
                        MemSrc <= LoadedMem;
                end if;
        end process;
 
 
 
        mem2 : process (clk)
        begin
 
                write <= M1M2.Store; -- to outside
                read <= '0';
 
                if rising_edge(clk) then
                        M2WB.WriteReg <= M1M2.WriteReg;
                        M2WB.MemToReg <= M1M2.MemToReg;
 
                        M2WB.IR <= M1M2.IR;
                        M2WB.AluRes <= M1M2.Address;
                        M2WB.MemWriteData <= MemSrc;
 
            if Stall = '1' then
                 M2WB.WriteReg  <=  M2WB.WriteReg ;
                 M2WB.MemToReg  <=  M2WB.MemToReg ;
                 M2WB.IR  <=  M2WB.IR ;
                 M2WB.AluRes  <=  M2WB.AluRes ;
                 M2WB.MemWriteData  <=  M2WB.MemWriteData ;
            end if;
                end if;
        end process;
 
        ----------------------------------------------------
    -- Write back
    ----------------------------------------------------
        WriteData <= M2WB.AluRes when M2WB.MemToReg = '0' else M2WB.MemWriteData;
 
end architecture;

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[/] [igor/] [trunk/] [processor/] [pl/] [leval2.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	atypic	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.numeric_std.all;`
4
5			`library work;`
6			`use work.leval2_pipelineregs.all;`
7			`use work.leval2_package.all;`
8
9			`entity leval2 is`
10			`port (`
11			`clk : in std_logic;`
12			`rst : in std_logic;`
13			`data_in : in std_logic_vector (BUS_BITS - 1 downto 0);`
14			`data_out : in std_logic_vector (BUS_BITS - 1 downto 0);`
15			`addr_bus : out std_logic_vector (ADDR_BITS - 1 downto 0);`
16			`iowait : in std_logic;`
17			`Sync : in std_logic;`
18			`read : out std_logic;`
19			`write : out std_logic;`
20			`led : out std_logic_vector(7 downto 0));`
21			`end entity;`
22
23
24			`architecture mixed of leval2 is`
25			`----------------------------------------------------`
26			`-- Pipeline register instances.`
27			`----------------------------------------------------`
28			`signal IFID : IFID_t;`
29			`signal IDEX : IDEX_t;`
30			`signal EXMEM : EXMEM_t;`
31			`signal M1M2 : M1M2_t;`
32			`signal M2WB : M2WB_t;`
33
34
35			`----------------------------------------------------`
36			`-- Signals from/internal to stages`
37			`----------------------------------------------------`
38
39			`-- Fetch`
40			`----------------------------------------------------------------------------`
41			`signal PC : std_logic_vector(MC_ADDR_BITS - 1 downto 0);`
42			`signal PCincremented : std_logic_vector(MC_ADDR_BITS - 1 downto 0);`
43			`-- signal PCmuxin : std_logic_vector(MC_ADDR_BITS - 1 downto 0);`
44			`signal InstrMemWe : std_logic;`
45			`signal InstrWriteData : std_logic_vector(MC_INSTR_BITS - 1 downto 0);`
46			`signal InstrWriteAddress : std_logic_vector(MC_ADDR_BITS - 1 downto 0);`
47			`signal Instruction : std_logic_vector(MC_INSTR_BITS - 1 downto 0);`
48
49			`-- Signals from decode stage`
50			`----------------------------------------------------------------------------`
51			`signal RegAddr1 : std_logic_vector(REGS_ADDR_BITS - 1 downto 0);`
52			`signal RegAddr2 : std_logic_vector(REGS_ADDR_BITS - 1 downto 0);`
53			`signal RegData1 : std_logic_vector(WORD_BITS - 1 downto 0);`
54			`signal RegData2 : std_logic_vector(WORD_BITS - 1 downto 0);`
55			`signal IndirReg1Sel : std_logic;`
56			`signal IndirReg2Sel : std_logic;`
57
58			`-- Signals from execute stage`
59			`----------------------------------------------------------------------------`
60			`signal Flags : std_logic_vector(STATUS_REG_BITS - 1 downto 0);`
61			`signal AluRes : std_logic_vector(OBJECT_SIZE - 1 downto 0);`
62			`signal AluIn1 : std_logic_vector(OBJECT_SIZe - 1 downto 0);`
63			`signal AluIn2 : std_logic_vector(OBJECT_SIZe - 1 downto 0);`
64
65
66			`-- Signals from/internal to memory 1 stage`
67			`----------------------------------------------------------------------------`
68			`signal Tag : std_logic_vector(CACHE_TAG_BITS - 1 downto 0);`
69			`signal BranchTaken : std_logic;`
70
71			`-- Signals from memory 2 stage`
72			`----------------------------------------------------------------------------`
73			`signal CacheHit : std_logic;`
74			`signal WriteCache : std_logic;`
75			`signal MemSrc : std_logic_vector(WORD_BITS - 1 downto 0);`
76			`signal CachedData : std_logic_vector(WORD_BITS - 1 downto 0);`
77
78			`-- Signals from write-back stage`
79			`----------------------------------------------------------------------------`
80			`signal WriteData : std_logic_vector(WORD_BITS - 1 downto 0);`
81
82			`-- Signals from control`
83			`----------------------------------------------------------------------------`
84			`signal PCMuxSel : std_logic_vector(1 downto 0);`
85			`signal AluOp : std_logic_vector(ALU_FUNCT_SIZE - 1 downto 0);`
86			`signal WriteReg : std_logic;`
87			`signal MemToReg : std_logic;`
88			`signal Store : std_logic;`
89			`signal AluIn2Src : std_logic;`
90			`signal IndirMux1 : std_logic;`
91			`signal IndirMux2 : std_logic;`
92			`signal Flush : std_logic;`
93			`signal Branch : std_logic;`
94			`signal Stall : std_logic;`
95
96
97			`-- Signals from forward`
98			`signal FwdMux1 : std_logic_vector(2 downto 0);`
99			`signal FwdMux2 : std_logic_vector(2 downto 0);`
100
101			`-- Signals from hazard`
102			`----------------------------------------------------------------------------`
103			`signal Hazard : std_logic;`
104
105			`-- Signals from outside`
106			`----------------------------------------------------------------------------`
107			`signal LoadedMem : std_logic_vector(WORD_BITS - 1 downto 0);`
108			`signal WritingMem : std_logic_vector(WORD_BITS - 1 downto 0);`
109			`-- signal Sync : std_logic;`
110			`signal MemWait : std_logic;`
111
112
113
114			`begin`
115			`----------------------------------------------------`
116			`-- Control unit`
117			`----------------------------------------------------`
118			`control_unit : entity control`
119			`port map (`
120			`IndirReg1Sel,`
121			`IndirReg2Sel,`
122			`PCMuxSel,`
123			`AluOp,`
124			`WriteReg,`
125			`Flush,`
126			`MemToReg,`
127			`IndirMux1,`
128			`IndirMux2,`
129			`Branch,`
130			`Store,`
131			`Stall,`
132			`Instruction(INSTR_OPCODE_START downto INSTR_OPCODE_END),`
133			`MemWait,`
134			`Sync,`
135			`BranchTaken,`
136			`Hazard`
137			`);`
138
139			`----------------------------------------------------`
140			`-- Forwarding unit`
141			`----------------------------------------------------`
142			`forwarding_unit : entity Forward`
143			`port map (`
144			`IDEX.AluIn2Src,`
145			`IDEX.Branch,`
146			`IDEX.IR(INSTR_REG1_START downto INSTR_REG1_END),`
147			`IDEX.IR(INSTR_REG2_START downto INSTR_REG2_END),`
148			`EXMEM.IR(INSTR_REG1_START downto INSTR_REG1_END),`
149			`EXMEM.IR(INSTR_REG2_START downto INSTR_REG2_END),`
150			`M2WB.IR(INSTR_REG1_START downto INSTR_REG1_END),`
151			`M2WB.IR(INSTR_REG2_START downto INSTR_REG2_END),`
152			`FwdMux1,`
153			`FwdMux2`
154			`);`
155
156			`----------------------------------------------------`
157			`-- Hazard unit`
158			`----------------------------------------------------`
159			`hazard_detection : entity Hazard`
160			`port map (`
161			`Instruction(INSTR_OPCODE_START downto INSTR_OPCODE_END),`
162			`Instruction(INSTR_REG1_START downto INSTR_REG1_END),`
163			`Instruction(INSTR_REG2_START downto INSTR_REG2_END),`
164			`IDEX.IR(INSTR_OPCODE_START downto INSTR_OPCODE_END),`
165			`IDEX.IR(INSTR_REG1_START downto INSTR_REG1_END),`
166			`IDEX.IR(INSTR_REG2_START downto INSTR_REG2_END),`
167			`EXMEM.IR(INSTR_OPCODE_START downto INSTR_OPCODE_END),`
168			`EXMEM.IR(INSTR_REG1_START downto INSTR_REG1_END),`
169			`EXMEM.IR(INSTR_REG2_START downto INSTR_REG2_END),`
170			`Hazard );`
171
172
173
174
175
176			`----------------------------------------------------`
177			`-- Fetch stage`
178			`----------------------------------------------------`
179			`PCincremented <= std_logic_vector(unsigned(PC) + 1);`
180
181			`instr_mem : entity rwmem`
182			`generic map (`
183			`INSTR_MEM_SIZE,`
184			`MC_ADDR_BITS,`
185			`MC_INSTR_BITS)`
186
187			`port map (`
188			`clk,`
189			`InstrMemWe,`
190			`PC,`
191			`InstrWriteAddress,`
192			`InstrWriteData,`
193			`Instruction);`
194
195			`instr_fetch : process (clk)`
196			`begin`
197			`if rising_edge(clk) then`
198			`if rst = '1' then`
199			`PC <= (others => '0');`
200			`elsif PCMuxSel = "00" then -- pipeline stall`
201			`PC <= PC;`
202			`IFID.PC <= PC;`
203			`elsif PCMUxSel = "01" then`
204			`PC <= EXMEM.AluRes(MC_ADDR_BITS - 1 downto 0);`
205			`IFID.PC <= EXMEM.AluRes(MC_ADDR_BITS - 1 downto 0);`
206			`else`
207			`PC <= PCIncremented;`
208			`IFID.PC <= PCIncremented;`
209			`end if;`
210
211			`if Flush = '1' then`
212			`IFID.PC <= (others => '0');`
213			`end if;`
214
215			`end if;`
216			`end process;`
217
218
219			`----------------------------------------------------`
220			`-- Decode stage`
221			`----------------------------------------------------`
222
223			`-- If we stored the indirect-bits in the previous cycle,`
224			`-- we now shall use the results from that register fetch`
225			`-- to address the new fetch, but avoid looping by anding with negated.`
226			`IndirReg1Sel <= not IDEX.IndirReg1bit and Instruction(INSTR_REG1_INDIR);`
227			`IndirReg2Sel <= not IDEX.IndirReg2bit and Instruction(INSTR_REG2_INDIR);`
228
229
230			`-- Indirection multiplexers`
231			`RegAddr1 <= Instruction(INSTR_REG1_START downto INSTR_REG1_END)`
232			`when IndirMux1 = '0'`
233			`else IDEX.IndirReg1;`
234
235			`RegAddr2 <= Instruction(INSTR_REG2_START downto INSTR_REG2_END)`
236			`when IndirMux2 = '0'`
237			`else IDEX.IndirReg2;`
238
239			`regfile : entity rrwmem`
240			`generic map (`
241			`memsize => REGS_SIZE,`
242			`addr_width => REGS_ADDR_BITS,`
243			`data_width => WORD_BITS,`
244			`initfile => SCRATCH_MEM_INIT)`
245			`port map (`
246			`clk,`
247			`M2WB.WriteReg,`
248			`RegAddr1,`
249			`RegAddr2,`
250			`M2WB.IR(INSTR_REG1_START downto INSTR_REG1_END),`
251			`WriteData,`
252			`RegData1,`
253			`RegData2);`
254
255			`instr_decode : process (clk)`
256			`begin`
257			`if rising_edge(clk) then`
258			`IDEX.WriteReg <= WriteReg;`
259			`IDEX.MemToReg <= MemToReg;`
260			`IDEX.Store <= Store;`
261			`IDEX.AluIn2Src <= AluIn2Src;`
262			`IDEX.AluOp <= AluOp;`
263			`IDEX.IndirReg1bit <= Instruction(INSTR_REG1_INDIR);`
264			`IDEX.IndirReg2bit <= Instruction(INSTR_REG2_INDIR);`
265			`IDEX.Branch <= Branch;`
266			`IDEX.IR <= Instruction;`
267			`IDEX.PC <= IFID.PC;`
268			`IDEX.Immediate <= sign_extend_18_26(Instruction(INSTR_IMM_START downto 0));`
269
270			`-- Flushing and stalling control paths.`
271			`if Flush = '1' then`
272			`IDEX.WriteReg <= '0';`
273			`IDEX.MemToReg <= '0';`
274			`IDEX.Store <= '0';`
275			`IDEX.AluIn2Src <= '0';`
276			`IDEX.AluOp <= ALU_PASS;`
277			`IDEX.IndirReg1bit <= '0';`
278			`IDEX.IndirReg2bit <= '0';`
279			`IDEX.Branch <= '0';`
280			`IDEX.IR <= (others=>'0');`
281			`IDEX.PC <= (others=>'0');`
282			`IDEX.Immediate <= (others=>'0');`
283			`elsif Stall = '1' then`
284			`IDEX.WriteReg <= IDEX.WriteReg;`
285			`IDEX.MemToReg <= IDEX.MemToReg;`
286			`IDEX.Store <= IDEX.Store;`
287			`IDEX.AluIn2Src <= IDEX.AluIn2Src;`
288			`IDEX.AluOp <= IDEX.AluOp;`
289			`IDEX.IndirReg1bit <= IDEX.IndirReg1bit;`
290			`IDEX.IndirReg2bit <= IDEX.IndirReg2bit;`
291			`IDEX.Branch <= IDEX.Branch;`
292			`IDEX.IR <= IDEX.IR;`
293			`IDEX.PC <= IDEX.PC;`
294			`IDEX.Immediate <= IDEX.Immediate;`
295			`end if;`
296			`end if;`
297			`end process;`
298
299
300
301			`----------------------------------------------------`
302			`-- Execution stage`
303			`----------------------------------------------------`
304			`-- Forwarding muxes`
305
306			`fwd_mux1 : process (FwdMux1, RegData1, IDEX.PC, M2WB.MemWriteData, M2WB.AluRes, EXMEM.AluRes)`
307			`begin`
308			`case FwdMux1 is`
309			`when FWD_BRANCH =>`
310			`AluIn1 <= IDEX.PC;`
311			`when FWD_REGDATA =>`
312			`AluIn1 <= RegData1;`
313			`when FWD_1_EXMEM_ALURES =>`
314			`AluIn1 <= EXMEM.AluRes;`
315			`when FWD_1_M2WB_ALURES =>`
316			`AluIn1 <= M2WB.AluRes;`
317			`when FWD_1_M2WB_MEMWRITEDATA =>`
318			`AluIn1 <= M2WB.MemWriteData;`
319			`when others =>`
320			`AluIn1 <= "00000000000000000000000000000000";`
321			`end case;`
322			`end process;`
323
324			`fwd_mux2 : process (FwdMux2, RegData2, IDEX.Immediate, M2WB.MemWriteData, M2WB.AluRes, EXMEM.AluRes)`
325			`begin`
326			`case FwdMux2 is`
327			`when FWD_2_IMMEDIATE =>`
328			`AluIn2 <= IDEX.Immediate;`
329			`when FWD_REGDATA =>`
330			`AluIn2 <= RegData2;`
331			`when FWD_2_EXMEM_ALURES =>`
332			`AluIn2 <= EXMEM.AluRes;`
333			`when FWD_2_M2WB_ALURES =>`
334			`AluIn2 <= M2WB.AluRes;`
335			`when FWD_2_M2WB_MEMWRITEDATA =>`
336			`AluIn2 <= M2WB.MemWriteData;`
337			`when others =>`
338			`AluIn2 <= "00000000000000000000000000000000";`
339			`end case;`
340			`end process;`
341
342
343
344			`main_alu : entity alu`
345			`port map (`
346			`AluIn1,`
347			`AluIn2,`
348			`IDEX.AluOp,`
349			`Flags,`
350			`AluRes`
351			`);`
352			`exec_stage : process (clk)`
353			`begin`
354			`if rising_edge(clk) then`
355			`EXMEM.WriteReg <= IDEX.WriteReg;`
356			`EXMEM.MemToReg <= IDEX.MemToReg;`
357			`EXMEM.Store <= IDEX.Store;`
358			`EXMEM.IR <= IDEX.IR;`
359			`EXMEM.AluRes <= AluRes;`
360			`EXMEM.MemWriteData <= RegData2;`
361			`end if;`
362			`end process;`
363
364
365
366			`----------------------------------------------------`
367			`-- Memory stage 1`
368			`----------------------------------------------------`
369
370
371			`tags : entity rwmem`
372			`generic map (`
373			`CACHE_LINES,`
374			`CACHE_INDEX_BITS,`
375			`CACHE_TAG_BITS)`
376
377			`port map (`
378			`clk,`
379			`WriteCache,`
380			`EXMEM.AluRes(CACHE_INDEX_POS downto 0),`
381			`M1M2.Address(CACHE_INDEX_POS downto 0) ,--write addr`
382			`M1M2.Tag,--write data`
383			`Tag);`
384
385
386			`data : entity rwmem`
387			`generic map (`
388			`CACHE_LINES,`
389			`CACHE_INDEX_BITS,`
390			`CACHE_DATA_BITS)`
391
392			`port map (`
393			`clk,`
394			`WriteCache,`
395			`EXMEM.AluRes(CACHE_INDEX_POS downto 0),`
396			`M1M2.Address(CACHE_INDEX_POS downto 0) ,--write addr`
397			`MemSrc,--write data`
398			`CachedData);`
399
400			`mem1 : process (clk)`
401			`begin`
402			`if rising_edge(clk) then`
403			`M1M2.WriteReg <= EXMEM.WriteReg;`
404			`M1M2.MemToReg <= EXMEM.MemToReg;`
405			`M1M2.Store <= EXMEM.Store;`
406
407			`M1M2.IR <= EXMEM.IR;`
408			`M1M2.Tag <= Tag;`
409			`M1M2.Address <= EXMEM.AluRes;`
410			`M1M2.Data <= CachedData;`
411			`M1M2.MemWriteData <= EXMEM.MemWriteData;`
412
413			`if Stall = '1' then`
414			`M1M2.WriteReg <= M1M2.WriteReg ;`
415			`M1M2.MemToReg <= M1M2.MemToReg ;`
416			`M1M2.Store <= M1M2.Store ;`
417
418			`M1M2.IR <= M1M2.IR ;`
419			`M1M2.Tag <= M1M2.Tag ;`
420			`M1M2.Address <= M1M2.Address ;`
421			`M1M2.Data <= M1M2.Data ;`
422			`M1M2.MemWriteData <= M1M2.MemWriteData ;`
423			`end if;`
424
425
426			`end if;`
427			`end process;`
428
429			`----------------------------------------------------`
430			`-- Memory stage 2`
431			`----------------------------------------------------`
432
433			`addr_bus <= M1M2.Address;`
434
435			`-- Tag compare`
436			`CacheHit <= '1' when M1M2.Tag = M1M2.Address(CACHE_TAG_START downto CACHE_TAG_END);`
437			`WriteCache <= not CacheHit;`
438
439			`LoadedMem <= data_in;`
440			`WritingMem <= data_out;`
441
442			`MemWait <= iowait; -- From outside.`
443
444			`-- The cache result mux`
445			`memmux : process(M1M2.Data, M1M2.MemWriteData, LoadedMem)`
446			`begin`
447			`if M1M2.Store = '1' then`
448			`MemSrc <= M1M2.Data; -- don't care: we're storing.`
449			`elsif M1M2.Store = '0' and CacheHit = '1' then -- cache hit`
450			`MemSrc <= M1M2.Data;`
451			`elsif MemToReg = '1' and CacheHit = '0' then -- cache miss`
452			`MemSrc <= LoadedMem;`
453			`end if;`
454			`end process;`
455
456
457
458			`mem2 : process (clk)`
459			`begin`
460
461			`write <= M1M2.Store; -- to outside`
462			`read <= '0';`
463
464			`if rising_edge(clk) then`
465			`M2WB.WriteReg <= M1M2.WriteReg;`
466			`M2WB.MemToReg <= M1M2.MemToReg;`
467
468			`M2WB.IR <= M1M2.IR;`
469			`M2WB.AluRes <= M1M2.Address;`
470			`M2WB.MemWriteData <= MemSrc;`
471
472			`if Stall = '1' then`
473			`M2WB.WriteReg <= M2WB.WriteReg ;`
474			`M2WB.MemToReg <= M2WB.MemToReg ;`
475			`M2WB.IR <= M2WB.IR ;`
476			`M2WB.AluRes <= M2WB.AluRes ;`
477			`M2WB.MemWriteData <= M2WB.MemWriteData ;`
478			`end if;`
479			`end if;`
480			`end process;`
481
482			`----------------------------------------------------`
483			`-- Write back`
484			`----------------------------------------------------`
485			`WriteData <= M2WB.AluRes when M2WB.MemToReg = '0' else M2WB.MemWriteData;`
486
487			`end architecture;`