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atypic |
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.leval2_constants.all;
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use work.all;
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entity whisk is
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port (
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clk : in std_logic;
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rst : in std_logic;
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data_in : in std_logic_vector (BUS_BITS - 1 downto 0);
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data_out : in std_logic_vector (BUS_BITS - 1 downto 0);
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addr_bus : in std_logic_vector (ADDR_BITS - 1 downto 0);
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iowait : in std_logic;
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sync : in std_logic;
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read : out std_logic;
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write : out std_logic;
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led : out std_logic);
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end entity;
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architecture rtl of whisk is
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-- signals from control
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signal ctrl_indir_reg1 : std_logic;
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signal ctrl_indir_reg2 : std_logic;
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signal ctrl_indir_idex_reg1 : std_logic;
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signal ctrl_indir_idex_reg2 : std_logic;
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signal ctrl_alu_funct : std_logic_vector(ALU_FUNCT_SIZE - 1 downto 0);
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signal ctrl_reg_write : std_logic;
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-- signals from stage 1 (fetch)
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signal ctrl_pc_mux : std_logic_vector(1 downto 0);
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signal fetched_instruction : std_logic_vector(MC_INSTR_BITS - 1 downto 0);
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signal branch_target : std_logic_vector(MC_ADDR_BITS - 1 downto 0);
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-- signals from stage 2 (decode)
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signal reg1_out : std_logic_vector(WORD_BITS - 1 downto 0);
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signal reg2_out : std_logic_vector(WORD_BITS - 1 downto 0);
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-- signal ctrl_regs_we : std_logic;
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signal ctrl_regs_addr_src_1 : std_logic;
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signal ctrl_regs_addr_src_2 : std_logic;
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signal immediate : std_logic_vector(IMM_SIZE - 1 downto 0);
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signal decode_reg_write : std_logic;
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signal alu_funct : std_logic_vector(ALU_FUNCT_SIZE - 1 downto 0);
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-- signals from stage 3 (exec)
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signal alu_result : std_logic_vector(WORD_BITS - 1 downto 0);
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signal alu_flags : std_logic_vector(STATUS_REG_BITS - 1 downto 0);
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signal exec_write_mem : std_logic;
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signal exec_read_mem : std_logic;
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signal exec_mem_ce : std_logic_vector(1 downto 0);
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signal exec_branch_taken : std_logic;
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signal exec_reg_write : std_logic; -- fwd to memory stage
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signal exec_reg2_out : std_logic_vector(WORD_BITS - 1 downto 0);
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-- signals from memory stage
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signal mem_mem_to_reg : std_logic;
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signal mem_reg_write : std_logic; -- register write control signal fed forward
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signal mem_reg_data : std_logic_vector(WORD_BITS - 1 downto 0); -- data from register to store
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signal mem_loaded_data : std_logic_vector(WORD_BITS - 1 downto 0);
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signal mem_alu_result : std_logic_vector(WORD_BITS - 1 downto 0);
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signal mem_write_mem : std_logic; -- signal out of memory stage to external mem
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signal mem_read_mem : std_logic; -- signal out of memory to external mem
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-- signals from write back
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signal wb_reg_write : std_logic; -- register write control signal piped forward
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signal wb_reg_data : std_logic_vector(WORD_BITS - 1 downto 0); -- data to write to register
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-- signals used from and to the data bus and to off-chip
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signal bus_read_data : std_logic_vector(WORD_BITS - 1 downto 0);
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signal mem_write_enable : std_logic; -- to external memory
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signal mem_write_data : std_logic_vector(WORD_BITS - 1 downto 0);
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signal databus : std_logic_vector(WORD_BITS - 1 downto 0); --to outside.
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signal mem_address : std_logic_vector(ADDR_BITS - 1 downto 0);
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signal memory_wait : std_logic;
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signal memory_ce : std_logic_vector(1 downto 0);
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signal avr_irq : std_logic;
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begin
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fetch_stage : entity instr_fetch
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port map (
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core_clk => clk,
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core_rst => rst,
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pc_mux => ctrl_pc_mux,
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instruction => fetched_instruction,
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branch_target => branch_target );
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decode_stage : entity instr_decode
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port map (
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instr => fetched_instruction,
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clk => clk,
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reg1 => reg1_out,
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reg2 => reg2_out,
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regs_addr_src_1 => ctrl_regs_addr_src_1,
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regs_addr_src_2 => ctrl_regs_addr_src_2,
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indir_reg1_sel => ctrl_indir_reg1,
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indir_reg2_sel => ctrl_indir_reg2,
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regs_data_in => wb_reg_data,
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ctrl_regs_we => ctrl_reg_write,
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wb_reg_write => mem_reg_write,
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ctrl_alu_funct => ctrl_alu_funct,
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reg_write => decode_reg_write,
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alu_funct => alu_funct);
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exec_stage : entity exec
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port map (
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clk => clk,
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operand1 => reg1_out,
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operand2 => reg2_out,
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imm => immediate,
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alu_res => alu_result,
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alu_flags => alu_flags,
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alu_funct => alu_funct,
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reg_write => decode_reg_write,
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branch_taken => exec_branch_taken,
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branch_target => branch_target,
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exec_reg_write => exec_reg_write,
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exec_reg2_out => exec_reg2_out);
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mem_stage : entity mem
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port map (
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-- Pipeline control signals
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clk => clk,
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exec_reg_write => exec_reg_write, -- Register write control (in)
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mem_reg_write => mem_reg_write, -- Register write control (out)
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mem_mem_to_reg => mem_mem_to_reg, -- Write to register when read
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address => alu_result(WORD_BITS - 1 downto 0), -- address to read/write
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data => exec_reg2_out, -- Data to write
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mem_loaded_data => mem_loaded_data,
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mem_alu_result => mem_alu_result,
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-- Bus IO
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mem_read_data => bus_read_data,
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mem_write_data => mem_write_data,
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mem_address => mem_address,
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write_mem => mem_write_mem,
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read_mem => mem_read_mem,
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memory_wait => memory_wait -- Stall signal from external memory
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);
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bus_interface : entity bidirbus
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port map (
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clk => clk,
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bidir => databus,
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oe => mem_write_enable,
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inp => mem_write_data,
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outp => bus_read_data);
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-- write back stage
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wb_reg_data <= mem_loaded_data when mem_mem_to_reg = '1' else mem_alu_result;
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wb_reg_write <= mem_reg_write;
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-- ctrl section
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control : entity control
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port map (
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indir_reg1 => ctrl_indir_reg1,
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indir_reg2 => ctrl_indir_reg2,
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indir_idex_reg1 => ctrl_indir_idex_reg1,
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indir_idex_reg2 => ctrl_indir_idex_reg2,
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pc_mux => ctrl_pc_mux,
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opcode => fetched_instruction(INSTR_OPCODE_START downto INSTR_OPCODE_END),
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idex_alu_funct => ctrl_alu_funct,
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reg_write => ctrl_reg_write,
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memory_wait => memory_wait,
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branch => exec_branch_taken);
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end architecture;
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