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[/] [iicmb/] [trunk/] [src/] [conditioner_mux.vhd] - Blame information for rev 4

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--==============================================================================
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--                                                                             |
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--    Project: IIC Multiple Bus Controller (IICMB)                             |
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--                                                                             |
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--    Module:  Multiplexer of I2C buses.                                       |
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--    Version:                                                                 |
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--             1.0,   April 29, 2016                                           |
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--                                                                             |
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--    Author:  Sergey Shuvalkin, (sshuv2@opencores.org)                        |
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--                                                                             |
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--==============================================================================
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--==============================================================================
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-- Copyright (c) 2016, Sergey Shuvalkin                                        |
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-- All rights reserved.                                                        |
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--                                                                             |
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-- Redistribution and use in source and binary forms, with or without          |
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-- modification, are permitted provided that the following conditions are met: |
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--                                                                             |
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-- 1. Redistributions of source code must retain the above copyright notice,   |
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--    this list of conditions and the following disclaimer.                    |
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-- 2. Redistributions in binary form must reproduce the above copyright        |
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--    notice, this list of conditions and the following disclaimer in the      |
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--    documentation and/or other materials provided with the distribution.     |
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--                                                                             |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE   |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE  |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE    |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR         |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF        |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS    |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN     |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)     |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE  |
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-- POSSIBILITY OF SUCH DAMAGE.                                                 |
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--==============================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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--==============================================================================
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entity conditioner_mux is
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  generic
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  (
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    ------------------------------------
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    g_bus_num :       positive range 1 to 16 := 1;          -- Number of separate I2C busses
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    g_f_clk   :       real           := 100000.0;   -- Frequency of 'clk' clock (in kHz)
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    g_f_scl_0 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #0 (in kHz)
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    g_f_scl_1 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #1 (in kHz)
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    g_f_scl_2 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #2 (in kHz)
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    g_f_scl_3 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #3 (in kHz)
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    g_f_scl_4 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #4 (in kHz)
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    g_f_scl_5 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #5 (in kHz)
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    g_f_scl_6 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #6 (in kHz)
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    g_f_scl_7 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #7 (in kHz)
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    g_f_scl_8 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #8 (in kHz)
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    g_f_scl_9 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #9 (in kHz)
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    g_f_scl_a :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #10 (in kHz)
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    g_f_scl_b :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #11 (in kHz)
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    g_f_scl_c :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #12 (in kHz)
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    g_f_scl_d :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #13 (in kHz)
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    g_f_scl_e :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #14 (in kHz)
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    g_f_scl_f :       real           :=    100.0    -- Frequency of 'SCL' clock of I2C bus #15 (in kHz)
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    ------------------------------------
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  );
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  port
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  (
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    ------------------------------------
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    clk       : in    std_logic;                            -- Clock
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    s_rst     : in    std_logic;                            -- Synchronous reset (active high)
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    ------------------------------------
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    ------------------------------------
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    -- Interface to controller:
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    bus_id    : in    natural range 0 to g_bus_num - 1;
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    --
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    busy      :   out std_logic := '0';                     -- Bus busy indication (busy = high)
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    --
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    scl_rx    :   out std_logic := '1';                     -- Conditioned I2C Clock
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    sda_rx    :   out std_logic := '1';                     -- Conditioned I2C Data
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    --
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    scl_d_rx  :   out std_logic := '1';                     -- Conditioned I2C Clock delayed for 1 'clk' cycle
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    --
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    scl_tx    : in    std_logic;                            -- I2C Clock from bit controller
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    sda_tx    : in    std_logic;                            -- I2C Data from bit controller
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    ------------------------------------
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    ------------------------------------
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    -- I2C interfaces:
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    scl_i     : in    std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs
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    sda_i     : in    std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs
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    scl_o     :   out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs
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    sda_o     :   out std_logic_vector(0 to g_bus_num - 1)  -- I2C Data outputs
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    ------------------------------------
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  );
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end entity conditioner_mux;
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--==============================================================================
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--==============================================================================
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architecture str of conditioner_mux is
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  type real_array is array (natural range <>) of real;
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  constant c_f_scl : real_array(0 to 15) := (g_f_scl_0, g_f_scl_1, g_f_scl_2, g_f_scl_3,
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                                             g_f_scl_4, g_f_scl_5, g_f_scl_6, g_f_scl_7,
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                                             g_f_scl_8, g_f_scl_9, g_f_scl_a, g_f_scl_b,
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                                             g_f_scl_c, g_f_scl_d, g_f_scl_e, g_f_scl_f);
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  ------------------------------------------------------------------------------
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  component conditioner is
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    generic
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    (
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      g_f_clk   :       real   := 100000.0;
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      g_f_scl   :       real   :=    100.0
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    );
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    port
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    (
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      clk       : in    std_logic;
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      s_rst     : in    std_logic;
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      busy      :   out std_logic;
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      scl_rx    :   out std_logic;
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      sda_rx    :   out std_logic;
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      scl_d_rx  :   out std_logic;
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      scl_tx    : in    std_logic;
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      sda_tx    : in    std_logic;
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      scl_i     : in    std_logic;
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      sda_i     : in    std_logic;
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      scl_o     :   out std_logic;
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      sda_o     :   out std_logic
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    );
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  end component conditioner;
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  ------------------------------------------------------------------------------
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  signal   scl_rx_y      : std_logic_vector(0 to g_bus_num - 1);
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  signal   sda_rx_y      : std_logic_vector(0 to g_bus_num - 1);
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  signal   scl_d_rx_y    : std_logic_vector(0 to g_bus_num - 1);
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  signal   busy_y        : std_logic_vector(0 to g_bus_num - 1);
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  signal   scl_tx_y      : std_logic_vector(0 to g_bus_num - 1) := (others => '1');
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  signal   sda_tx_y      : std_logic_vector(0 to g_bus_num - 1) := (others => '1');
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begin
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  ------------------------------------------------------------------------------
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  process(clk)
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  begin
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    if rising_edge(clk) then
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      if (s_rst = '1') then
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        busy     <= '0';
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        scl_rx   <= '1';
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        sda_rx   <= '1';
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        scl_d_rx <= '1';
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      else
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        busy     <= busy_y(bus_id);
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        scl_rx   <= scl_rx_y(bus_id);
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        sda_rx   <= sda_rx_y(bus_id);
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        scl_d_rx <= scl_d_rx_y(bus_id);
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      end if;
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    end if;
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  end process;
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  ------------------------------------------------------------------------------
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  --****************************************************************************
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  scl_sda_gen:
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  for i in 0 to g_bus_num - 1 generate
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    ----------------------------------------------------------------------------
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    conditioner_inst0 : conditioner
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      generic map
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      (
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        g_f_clk   => g_f_clk,
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        g_f_scl   => c_f_scl(i)
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      )
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      port map
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      (
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        clk       => clk,
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        s_rst     => s_rst,
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        busy      => busy_y(i),
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        scl_rx    => scl_rx_y(i),
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        sda_rx    => sda_rx_y(i),
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        scl_d_rx  => scl_d_rx_y(i),
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        scl_tx    => scl_tx_y(i),
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        sda_tx    => sda_tx_y(i),
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        scl_i     => scl_i(i),
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        sda_i     => sda_i(i),
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        scl_o     => scl_o(i),
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        sda_o     => sda_o(i)
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      );
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    ----------------------------------------------------------------------------
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    ----------------------------------------------------------------------------
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    process(clk)
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    begin
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      if rising_edge(clk) then
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        if (s_rst = '1') then
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          scl_tx_y(i) <= '1';
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          sda_tx_y(i) <= '1';
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        else
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          if (i = bus_id) then
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            scl_tx_y(i) <= scl_tx;
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            sda_tx_y(i) <= sda_tx;
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          else
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            scl_tx_y(i) <= '1';
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            sda_tx_y(i) <= '1';
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          end if;
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        end if;
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      end if;
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    end process;
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    ----------------------------------------------------------------------------
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  end generate scl_sda_gen;
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  --****************************************************************************
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end architecture str;
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--==============================================================================
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