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--==============================================================================
--                                                                             |
--    Project: IIC Multiple Bus Controller (IICMB)                             |
--                                                                             |
--    Module:  Bit layer FSM (master mode).                                    |
--    Version:                                                                 |
--             1.0,   April 29, 2016                                           |
--                                                                             |
--    Author:  Sergey Shuvalkin, (sshuv2@opencores.org)                        |
--                                                                             |
--==============================================================================
--==============================================================================
-- Copyright (c) 2016, Sergey Shuvalkin                                        |
-- All rights reserved.                                                        |
--                                                                             |
-- Redistribution and use in source and binary forms, with or without          |
-- modification, are permitted provided that the following conditions are met: |
--                                                                             |
-- 1. Redistributions of source code must retain the above copyright notice,   |
--    this list of conditions and the following disclaimer.                    |
-- 2. Redistributions in binary form must reproduce the above copyright        |
--    notice, this list of conditions and the following disclaimer in the      |
--    documentation and/or other materials provided with the distribution.     |
--                                                                             |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE   |
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE  |
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE    |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR         |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF        |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS    |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN     |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)     |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE  |
-- POSSIBILITY OF SUCH DAMAGE.                                                 |
--==============================================================================
 
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.iicmb_int_pkg.all;
 
 
--==============================================================================
entity mbit is
  generic
  (
    g_bus_num :       positive range 1 to 16 := 1;  -- Number of connected I2C buses
    g_f_clk   :       real           := 100000.0;   -- Frequency of 'clk' clock (in kHz)
    g_f_scl_0 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #0 (in kHz)
    g_f_scl_1 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #1 (in kHz)
    g_f_scl_2 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #2 (in kHz)
    g_f_scl_3 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #3 (in kHz)
    g_f_scl_4 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #4 (in kHz)
    g_f_scl_5 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #5 (in kHz)
    g_f_scl_6 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #6 (in kHz)
    g_f_scl_7 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #7 (in kHz)
    g_f_scl_8 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #8 (in kHz)
    g_f_scl_9 :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #9 (in kHz)
    g_f_scl_a :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #10 (in kHz)
    g_f_scl_b :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #11 (in kHz)
    g_f_scl_c :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #12 (in kHz)
    g_f_scl_d :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #13 (in kHz)
    g_f_scl_e :       real           :=    100.0;   -- Frequency of 'SCL' clock of I2C bus #14 (in kHz)
    g_f_scl_f :       real           :=    100.0    -- Frequency of 'SCL' clock of I2C bus #15 (in kHz)
  );
  port
  (
    ------------------------------------
    clk       : in    std_logic;                    -- Clock
    s_rst     : in    std_logic;                    -- Synchronous reset (active high)
    ------------------------------------
    ------------------------------------
    fsm_state :   out std_logic_vector(3 downto 0); -- FSM state
    bus_id    : in    natural range 0 to g_bus_num - 1; -- I2C Bus ID
    ------------------------------------
    ------------------------------------
    mbc_wr    : in    std_logic;                    -- Bit command write indication (active high)
    mbc       : in    mbc_type;                     -- Bit command
    ------------------------------------
    ------------------------------------
    mbr_wr    :   out std_logic      := '0';        -- Bit command response write indication (active high)
    mbr       :   out mbr_type       := mbr_done;   -- Bit command response
    ------------------------------------
    ------------------------------------
    scl_i     : in    std_logic;                    -- I2C Clock input
    sda_i     : in    std_logic;                    -- I2C Data input
    scl_i_d   : in    std_logic;                    -- I2C Clock input delayed for 1 clock cycle
    scl_o     :   out std_logic      := '1';        -- I2C Clock output
    sda_o     :   out std_logic      := '1'         -- I2C Data output
    ------------------------------------
  );
end entity mbit;
--==============================================================================
 
--==============================================================================
architecture rtl of mbit is
 
  type real_array is array (natural range <>) of real;
  constant c_f_scl : real_array(0 to 15) := (g_f_scl_0, g_f_scl_1, g_f_scl_2, g_f_scl_3,
                                             g_f_scl_4, g_f_scl_5, g_f_scl_6, g_f_scl_7,
                                             g_f_scl_8, g_f_scl_9, g_f_scl_a, g_f_scl_b,
                                             g_f_scl_c, g_f_scl_d, g_f_scl_e, g_f_scl_f);
 
  type timing_parameters_type is record
    max_cnt       : integer; -- Minimum number of 'clk' cycles in single 'SCL' cycle
    fe_cnt        : integer; -- Time for falling edge of 'SCL'
    t_hd_sta_cnt  : integer; -- Hold time (repeated) Start condition
    t_vd_dat_cnt  : integer; -- Data valid time
    t_high_cnt    : integer; -- 'SCL' high time
    t_su_sto_cnt  : integer; -- Set-up time for Stop condition
    t_su_sta_cnt  : integer; -- Set-up time for a repeated Start condition
    t_su_dat_cnt  : integer; -- Data set-up time
  end record;
 
  type timing_parameters_type_array is array (0 to g_bus_num - 1) of timing_parameters_type;
 
  ------------------------------------------------------------------------------
  function get_tp(a_f_clk : real; a_f_scl : real_array(0 to 15)) return timing_parameters_type_array is
    variable ret        : timing_parameters_type_array;
    variable v_t_scl    : integer;
    variable v_t_high   : integer;
    variable v_t_low    : integer;
    variable v_t_vd_dat : integer;
  begin
    for i in ret'range loop
      v_t_scl             := integer((a_f_clk/a_f_scl(i)) + 0.4999);   -- number of 'clk' periods in an 'SCL' period
      if (a_f_scl(i) <= 100.0) then
        v_t_high            := integer(real(v_t_scl)*0.401);             -- 'SCL' high time
        v_t_low             := integer(real(v_t_scl)*0.47);              -- 'SCL' low time
      else
        v_t_high            := integer(real(v_t_scl)*0.241);             -- 'SCL' high time
        v_t_low             := integer(real(v_t_scl)*0.52);              -- 'SCL' low time
      end if;
      v_t_vd_dat          := integer((a_f_clk*(0.5/1000.0)) + 0.4999);
      --
      ret(i).max_cnt      := v_t_scl - 1;
      ret(i).fe_cnt       := v_t_low - v_t_vd_dat + v_t_high - 1;
      ret(i).t_hd_sta_cnt := v_t_high - 1;
      ret(i).t_vd_dat_cnt := v_t_vd_dat - 1;
      ret(i).t_high_cnt   := v_t_high - 1;
      ret(i).t_su_sto_cnt := v_t_high - 1;
      ret(i).t_su_sta_cnt := v_t_low - 1;
      ret(i).t_su_dat_cnt := v_t_low - v_t_vd_dat - 1;
    end loop;
    return ret;
  end function get_tp;
  ------------------------------------------------------------------------------
 
  ------------------------------------------------------------------------------
  function get_max_cnt(a : timing_parameters_type_array) return integer is
    variable ret        : integer := 0;
  begin
    for i in a'range loop
      if (ret < a(i).max_cnt) then
        ret := a(i).max_cnt;
      end if;
    end loop;
    return ret;
  end function get_max_cnt;
  ------------------------------------------------------------------------------
 
  constant c_tp            : timing_parameters_type_array := get_tp(g_f_clk, c_f_scl);
  constant c_max_cnt       : integer := get_max_cnt(c_tp);
 
  type state_type is
    (
      s_idle,      -- Idle
      --
      s_start_a,   -- Start condition generating
      s_start_b,   -- Start condition generating
      s_start_c,   -- Start condition generating
      --
      s_rw_a,      -- Bit Read/Write
      s_rw_b,      -- Bit Read/Write
      s_rw_c,      -- Bit Read/Write
      s_rw_d,      -- Bit Read/Write
      s_rw_e,      -- Bit Read/Write
      --
      s_stop_a,    -- Stop condition generating
      s_stop_b,    -- Stop condition generating
      s_stop_c,    -- Stop condition generating
      --
      s_rstart_a,  -- Preparation for Repeated Start
      s_rstart_b,  -- Preparation for Repeated Start
      s_rstart_c   -- Preparation for Repeated Start
    );
 
  ------------------------------------------------------------------------------
  -- Conversion from 'state_type' to 'std_logic_vector(3 downto 0)'
  function to_std_logic_vector(a : state_type) return std_logic_vector is
  begin
    case (a) is
      when s_idle      => return "0000";
      when s_start_a   => return "0001";
      when s_start_b   => return "0010";
      when s_start_c   => return "0011";
      when s_rw_a      => return "0100";
      when s_rw_b      => return "0101";
      when s_rw_c      => return "0110";
      when s_rw_d      => return "0111";
      when s_rw_e      => return "1000";
      when s_stop_a    => return "1001";
      when s_stop_b    => return "1010";
      when s_stop_c    => return "1011";
      when s_rstart_a  => return "1100";
      when s_rstart_b  => return "1101";
      when s_rstart_c  => return "1110";
    end case;
  end function to_std_logic_vector;
  ------------------------------------------------------------------------------
 
  signal   state           : state_type                   := s_idle; -- FSM state
  signal   cnt             : integer range 0 to c_max_cnt := 0;      -- Counter of clock cycles
  signal   d_reg           : std_logic                    := '0';    -- Output data bit register
  signal   r_reg           : std_logic                    := '0';    -- Read operation indication
  signal   i_reg           : std_logic                    := '0';    -- Input data bit register
 
  signal   scl_cnt         : integer range 0 to c_max_cnt := 0;      -- Counter of cycles when scl is stable
 
  -- Timing parameters:
  signal   max_cnt         : integer range 0 to c_max_cnt := c_tp(0).max_cnt;
  signal   fe_cnt          : integer range 0 to c_max_cnt := c_tp(0).fe_cnt;
  signal   t_hd_sta_cnt    : integer range 0 to c_max_cnt := c_tp(0).t_hd_sta_cnt;
  signal   t_vd_dat_cnt    : integer range 0 to c_max_cnt := c_tp(0).t_vd_dat_cnt;
  signal   t_high_cnt      : integer range 0 to c_max_cnt := c_tp(0).t_high_cnt;
  signal   t_su_sto_cnt    : integer range 0 to c_max_cnt := c_tp(0).t_su_sto_cnt;
  signal   t_su_sta_cnt    : integer range 0 to c_max_cnt := c_tp(0).t_su_sta_cnt;
  signal   t_su_dat_cnt    : integer range 0 to c_max_cnt := c_tp(0).t_su_dat_cnt;
 
begin
 
  fsm_state <= to_std_logic_vector(state);
 
  ------------------------------------------------------------------------------
  -- Changing timing parameters:
  tp_proc:
  process(clk)
  begin
    if rising_edge(clk) then
      if (s_rst = '1') then
        max_cnt      <= c_tp(0).max_cnt;
        fe_cnt       <= c_tp(0).fe_cnt;
        t_hd_sta_cnt <= c_tp(0).t_hd_sta_cnt;
        t_vd_dat_cnt <= c_tp(0).t_vd_dat_cnt;
        t_high_cnt   <= c_tp(0).t_high_cnt;
        t_su_sto_cnt <= c_tp(0).t_su_sto_cnt;
        t_su_sta_cnt <= c_tp(0).t_su_sta_cnt;
        t_su_dat_cnt <= c_tp(0).t_su_dat_cnt;
      else
        max_cnt      <= c_tp(bus_id).max_cnt;
        fe_cnt       <= c_tp(bus_id).fe_cnt;
        t_hd_sta_cnt <= c_tp(bus_id).t_hd_sta_cnt;
        t_vd_dat_cnt <= c_tp(bus_id).t_vd_dat_cnt;
        t_high_cnt   <= c_tp(bus_id).t_high_cnt;
        t_su_sto_cnt <= c_tp(bus_id).t_su_sto_cnt;
        t_su_sta_cnt <= c_tp(bus_id).t_su_sta_cnt;
        t_su_dat_cnt <= c_tp(bus_id).t_su_dat_cnt;
      end if;
    end if;
  end process tp_proc;
  ------------------------------------------------------------------------------
 
  ------------------------------------------------------------------------------
  -- Counting how long 'scl_i' input remains stable
  scl_cnt_proc:
  process(clk)
  begin
    if rising_edge(clk) then
      if (s_rst = '1') then
        scl_cnt <= 0;
      else
        if (scl_i_d /= scl_i) then
          scl_cnt <= 1;
        elsif (scl_cnt < max_cnt) then
          scl_cnt <= scl_cnt + 1;
        else
          scl_cnt <= max_cnt;
        end if;
      end if;
    end if;
  end process scl_cnt_proc;
  ------------------------------------------------------------------------------
 
  ------------------------------------------------------------------------------
  -- Main Finite State Machine:
  process(clk)
  begin
    if rising_edge(clk) then
      if (s_rst = '1') then
        state   <= s_idle;
        d_reg   <= '0';
        i_reg   <= '0';
        r_reg   <= '0';
        cnt     <= 0;
        mbr_wr  <= '0';
        mbr     <= mbr_done;
      else
        -- Defaults:
        if (cnt < max_cnt) then
          cnt     <= cnt + 1;
        else
          cnt     <= max_cnt;
        end if;
        mbr_wr  <= '0';
        ------
 
        case state is
          -- 'Idle' state ----------------------------------
          when s_idle =>
            if (mbc_wr = '1') then
              case (mbc) is
                when mbc_start =>
                  state  <= s_start_a;
                when mbc_stop =>
                  assert false report "Stop command without Start command!" severity error;
                  mbr_wr <= '1';
                  mbr    <= mbr_done;
                when others =>
                  assert false report "In 'Idle' state only Start command allowed!" severity error;
                  mbr_wr <= '1';
                  mbr    <= mbr_error;
              end case;
              cnt    <= 0;
            end if;
          -- 'Idle' state ----------------------------------
 
          -- 'Start A' state -------------------------------
          when s_start_a =>
            if (scl_i = '0')or(cnt = t_hd_sta_cnt) then -- t_{HD;STA} >= 4.0 us
              state  <= s_start_b;
            end if;
          -- 'Start A' state -------------------------------
 
          -- 'Start B' state -------------------------------
          when s_start_b =>
            if (scl_i_d = '0')and(scl_cnt > t_vd_dat_cnt) then -- t_{VD;DAT} <= 3.45 us, t_{HD;DAT} >= 0 us;
              state  <= s_start_c;
              mbr_wr <= '1';
              mbr    <= mbr_done;
            end if;
          -- 'Start B' state -------------------------------
 
          -- 'Start C' state -------------------------------
          when s_start_c =>
            if (mbc_wr = '1') then
              case (mbc) is
                when mbc_write_0 =>
                  state  <= s_rw_a;
                  d_reg  <= '0'; -- data
                  r_reg  <= '0'; -- read indication
                when mbc_write_1 =>
                  state  <= s_rw_a;
                  d_reg  <= '1'; -- data
                  r_reg  <= '0'; -- read indication
                when mbc_read =>
                  state  <= s_rw_a;
                  d_reg  <= '1'; -- data
                  r_reg  <= '1'; -- read indication
                when mbc_stop =>
                  state  <= s_stop_a;
                when mbc_start =>
                  -- Second 'Start' command coming immediately after the first
                  -- one is ignored without an 'Error' response.
                  assert false report "Second Start command!" severity error;
                  mbr_wr <= '1';
                  mbr    <= mbr_done;
              end case;
              cnt    <= 0;
            end if;
          -- 'Start C' state -------------------------------
 
          -- 'Read/Write A' state --------------------------
          when s_rw_a =>
            if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us
              state  <= s_rw_b;
            end if;
          -- 'Read/Write A' state --------------------------
 
          -- 'Read/Write B' state --------------------------
          when s_rw_b =>
            if (scl_i = '1') then
              state  <= s_rw_c;
            end if;
          -- 'Read/Write B' state --------------------------
 
          -- 'Read/Write C' state --------------------------
          when s_rw_c =>
            if (scl_i = '0')or((scl_cnt > t_high_cnt)and(cnt >= fe_cnt)) then -- t_{HIGH} >= 4.0 us;
              state  <= s_rw_d;
              i_reg  <= sda_i;
            end if;
            if (scl_i = '1')and(r_reg = '0')and(sda_i /= d_reg) then
              mbr_wr <= '1';
              mbr    <= mbr_arb_lost; -- Arbitration lost
              state  <= s_idle;
            end if;
          -- 'Read/Write C' state --------------------------
 
          -- 'Read/Write D' state --------------------------
          when s_rw_d =>
            if (scl_i_d = '0')and(scl_cnt > t_vd_dat_cnt)and(cnt = max_cnt) then -- t_{VD;DAT} <= 3.45 us, t_{HD;DAT} >= 0 us;
              state  <= s_rw_e;
              mbr_wr <= '1';
              if (r_reg = '0') then
                mbr    <= mbr_done;     -- Successfull write
              else
                if (i_reg = '0') then
                  mbr    <= mbr_bit_0;    -- Bit 0 received
                else
                  mbr    <= mbr_bit_1;    -- Bit 1 received
                end if;
              end if;
            end if;
          -- 'Read/Write D' state --------------------------
 
          -- 'Read/Write E' state --------------------------
          when s_rw_e =>
            if (mbc_wr = '1') then
              case (mbc) is
                when mbc_write_0 =>
                  state  <= s_rw_a;
                  d_reg  <= '0'; -- data
                  r_reg  <= '0'; -- read indication
                when mbc_write_1 =>
                  state  <= s_rw_a;
                  d_reg  <= '1'; -- data
                  r_reg  <= '0'; -- read indication
                when mbc_read =>
                  state  <= s_rw_a;
                  d_reg  <= '1'; -- data
                  r_reg  <= '1'; -- read indication
                when mbc_start =>
                  state  <= s_rstart_a;
                when mbc_stop =>
                  state  <= s_stop_a;
              end case;
              cnt    <= 0;
            end if;
          -- 'Read/Write E' state --------------------------
 
          -- 'Stop A' state --------------------------------
          when s_stop_a =>
            if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us
              state  <= s_stop_b;
            end if;
          -- 'Stop A' state --------------------------------
 
          -- 'Stop B' state --------------------------------
          when s_stop_b =>
            if (scl_i = '1') then
              state  <= s_stop_c;
              cnt    <= 0;
            end if;
          -- 'Stop B' state --------------------------------
 
          -- 'Stop C' state --------------------------------
          when s_stop_c =>
            if (cnt > t_su_sto_cnt) then -- t_{SU;STO} >= 4.0 us
              state  <= s_idle;
              mbr_wr <= '1';
              mbr    <= mbr_done;
              cnt    <= 0;
            end if;
          -- 'Stop C' state --------------------------------
 
          -- 'Repeated Start A' state ----------------------
          when s_rstart_a =>
            if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us
              state  <= s_rstart_b;
            end if;
          -- 'Repeated Start A' state ----------------------
 
          -- 'Repeated Start B' state ----------------------
          when s_rstart_b =>
            if (scl_i = '1') then
              state  <= s_rstart_c;
            end if;
          -- 'Repeated Start B' state ----------------------
 
          -- 'Repeated Start C' state ----------------------
          when s_rstart_c =>
            if (scl_i_d = '0')or((scl_cnt > t_su_sta_cnt)and(cnt = max_cnt)) then -- t_{SU;STA} >= 4.7 us
              state  <= s_start_a;
              cnt    <= 0;
            end if;
            if (scl_i = '1')and(sda_i = '0') then
              mbr_wr <= '1';
              mbr    <= mbr_arb_lost; -- Arbitration lost
              state  <= s_idle;
            end if;
          -- 'Repeated Start C' state ----------------------
        end case;
      end if;
    end if;
  end process;
  ------------------------------------------------------------------------------
 
  ------------------------------------------------------------------------------
  scl_sda_proc:
  process(clk)
  begin
    if rising_edge(clk) then
      if (s_rst = '1') then
        scl_o <= '1';
        sda_o <= '1';
      else
        case state is
          when s_idle     => sda_o <= '1';   scl_o <= '1';
          when s_start_a  => sda_o <= '0';   scl_o <= '1';
          when s_start_b  => sda_o <= '0';   scl_o <= '0';
          when s_start_c  => sda_o <= '0';   scl_o <= '0';
          when s_rw_a     => sda_o <= d_reg; scl_o <= '0';
          when s_rw_b     => sda_o <= d_reg; scl_o <= '1';
          when s_rw_c     => sda_o <= d_reg; scl_o <= '1';
          when s_rw_d     => sda_o <= d_reg; scl_o <= '0';
          when s_rw_e     => sda_o <= d_reg; scl_o <= '0';
          when s_stop_a   => sda_o <= '0';   scl_o <= '0';
          when s_stop_b   => sda_o <= '0';   scl_o <= '1';
          when s_stop_c   => sda_o <= '0';   scl_o <= '1';
          when s_rstart_a => sda_o <= '1';   scl_o <= '0';
          when s_rstart_b => sda_o <= '1';   scl_o <= '1';
          when s_rstart_c => sda_o <= '1';   scl_o <= '1';
        end case;
      end if;
    end if;
  end process scl_sda_proc;
  ------------------------------------------------------------------------------
 
end architecture rtl;
--==============================================================================
 

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[/] [iicmb/] [trunk/] [src/] [mbit.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sshuv2
2			`--==============================================================================`
3			`-- \|`
4			`-- Project: IIC Multiple Bus Controller (IICMB) \|`
5			`-- \|`
6			`-- Module: Bit layer FSM (master mode). \|`
7			`-- Version: \|`
8			`-- 1.0, April 29, 2016 \|`
9			`-- \|`
10			`-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) \|`
11			`-- \|`
12			`--==============================================================================`
13			`--==============================================================================`
14			`-- Copyright (c) 2016, Sergey Shuvalkin \|`
15			`-- All rights reserved. \|`
16			`-- \|`
17			`-- Redistribution and use in source and binary forms, with or without \|`
18			`-- modification, are permitted provided that the following conditions are met: \|`
19			`-- \|`
20			`-- 1. Redistributions of source code must retain the above copyright notice, \|`
21			`-- this list of conditions and the following disclaimer. \|`
22			`-- 2. Redistributions in binary form must reproduce the above copyright \|`
23			`-- notice, this list of conditions and the following disclaimer in the \|`
24			`-- documentation and/or other materials provided with the distribution. \|`
25			`-- \|`
26			`-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" \|`
27			`-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \|`
28			`-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \|`
29			`-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE \|`
30			`-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR \|`
31			`-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \|`
32			`-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \|`
33			`-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \|`
34			`-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \|`
35			`-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE \|`
36			`-- POSSIBILITY OF SUCH DAMAGE. \|`
37			`--==============================================================================`
38
39
40			`library ieee;`
41			`use ieee.std_logic_1164.all;`
42
43			`use work.iicmb_int_pkg.all;`
44
45
46			`--==============================================================================`
47			`entity mbit is`
48			`generic`
49			`(`
50			`g_bus_num : positive range 1 to 16 := 1; -- Number of connected I2C buses`
51			`g_f_clk : real := 100000.0; -- Frequency of 'clk' clock (in kHz)`
52			`g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz)`
53			`g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz)`
54			`g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz)`
55			`g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz)`
56			`g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz)`
57			`g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz)`
58			`g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz)`
59			`g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz)`
60			`g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz)`
61			`g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz)`
62			`g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz)`
63			`g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz)`
64			`g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz)`
65			`g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz)`
66			`g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz)`
67			`g_f_scl_f : real := 100.0 -- Frequency of 'SCL' clock of I2C bus #15 (in kHz)`
68			`);`
69			`port`
70			`(`
71			`------------------------------------`
72			`clk : in std_logic; -- Clock`
73			`s_rst : in std_logic; -- Synchronous reset (active high)`
74			`------------------------------------`
75			`------------------------------------`
76			`fsm_state : out std_logic_vector(3 downto 0); -- FSM state`
77			`bus_id : in natural range 0 to g_bus_num - 1; -- I2C Bus ID`
78			`------------------------------------`
79			`------------------------------------`
80			`mbc_wr : in std_logic; -- Bit command write indication (active high)`
81			`mbc : in mbc_type; -- Bit command`
82			`------------------------------------`
83			`------------------------------------`
84			`mbr_wr : out std_logic := '0'; -- Bit command response write indication (active high)`
85			`mbr : out mbr_type := mbr_done; -- Bit command response`
86			`------------------------------------`
87			`------------------------------------`
88			`scl_i : in std_logic; -- I2C Clock input`
89			`sda_i : in std_logic; -- I2C Data input`
90			`scl_i_d : in std_logic; -- I2C Clock input delayed for 1 clock cycle`
91			`scl_o : out std_logic := '1'; -- I2C Clock output`
92			`sda_o : out std_logic := '1' -- I2C Data output`
93			`------------------------------------`
94			`);`
95			`end entity mbit;`
96			`--==============================================================================`
97
98			`--==============================================================================`
99			`architecture rtl of mbit is`
100
101			`type real_array is array (natural range <>) of real;`
102			`constant c_f_scl : real_array(0 to 15) := (g_f_scl_0, g_f_scl_1, g_f_scl_2, g_f_scl_3,`
103			`g_f_scl_4, g_f_scl_5, g_f_scl_6, g_f_scl_7,`
104			`g_f_scl_8, g_f_scl_9, g_f_scl_a, g_f_scl_b,`
105			`g_f_scl_c, g_f_scl_d, g_f_scl_e, g_f_scl_f);`
106
107			`type timing_parameters_type is record`
108			`max_cnt : integer; -- Minimum number of 'clk' cycles in single 'SCL' cycle`
109			`fe_cnt : integer; -- Time for falling edge of 'SCL'`
110			`t_hd_sta_cnt : integer; -- Hold time (repeated) Start condition`
111			`t_vd_dat_cnt : integer; -- Data valid time`
112			`t_high_cnt : integer; -- 'SCL' high time`
113			`t_su_sto_cnt : integer; -- Set-up time for Stop condition`
114			`t_su_sta_cnt : integer; -- Set-up time for a repeated Start condition`
115			`t_su_dat_cnt : integer; -- Data set-up time`
116			`end record;`
117
118			`type timing_parameters_type_array is array (0 to g_bus_num - 1) of timing_parameters_type;`
119
120			`------------------------------------------------------------------------------`
121			`function get_tp(a_f_clk : real; a_f_scl : real_array(0 to 15)) return timing_parameters_type_array is`
122			`variable ret : timing_parameters_type_array;`
123			`variable v_t_scl : integer;`
124			`variable v_t_high : integer;`
125			`variable v_t_low : integer;`
126			`variable v_t_vd_dat : integer;`
127			`begin`
128			`for i in ret'range loop`
129			`v_t_scl := integer((a_f_clk/a_f_scl(i)) + 0.4999); -- number of 'clk' periods in an 'SCL' period`
130			`if (a_f_scl(i) <= 100.0) then`
131			`v_t_high := integer(real(v_t_scl)*0.401); -- 'SCL' high time`
132			`v_t_low := integer(real(v_t_scl)*0.47); -- 'SCL' low time`
133			`else`
134			`v_t_high := integer(real(v_t_scl)*0.241); -- 'SCL' high time`
135			`v_t_low := integer(real(v_t_scl)*0.52); -- 'SCL' low time`
136			`end if;`
137			`v_t_vd_dat := integer((a_f_clk*(0.5/1000.0)) + 0.4999);`
138			`--`
139			`ret(i).max_cnt := v_t_scl - 1;`
140			`ret(i).fe_cnt := v_t_low - v_t_vd_dat + v_t_high - 1;`
141			`ret(i).t_hd_sta_cnt := v_t_high - 1;`
142			`ret(i).t_vd_dat_cnt := v_t_vd_dat - 1;`
143			`ret(i).t_high_cnt := v_t_high - 1;`
144			`ret(i).t_su_sto_cnt := v_t_high - 1;`
145			`ret(i).t_su_sta_cnt := v_t_low - 1;`
146			`ret(i).t_su_dat_cnt := v_t_low - v_t_vd_dat - 1;`
147			`end loop;`
148			`return ret;`
149			`end function get_tp;`
150			`------------------------------------------------------------------------------`
151
152			`------------------------------------------------------------------------------`
153			`function get_max_cnt(a : timing_parameters_type_array) return integer is`
154			`variable ret : integer := 0;`
155			`begin`
156			`for i in a'range loop`
157			`if (ret < a(i).max_cnt) then`
158			`ret := a(i).max_cnt;`
159			`end if;`
160			`end loop;`
161			`return ret;`
162			`end function get_max_cnt;`
163			`------------------------------------------------------------------------------`
164
165			`constant c_tp : timing_parameters_type_array := get_tp(g_f_clk, c_f_scl);`
166			`constant c_max_cnt : integer := get_max_cnt(c_tp);`
167
168			`type state_type is`
169			`(`
170			`s_idle, -- Idle`
171			`--`
172			`s_start_a, -- Start condition generating`
173			`s_start_b, -- Start condition generating`
174			`s_start_c, -- Start condition generating`
175			`--`
176			`s_rw_a, -- Bit Read/Write`
177			`s_rw_b, -- Bit Read/Write`
178			`s_rw_c, -- Bit Read/Write`
179			`s_rw_d, -- Bit Read/Write`
180			`s_rw_e, -- Bit Read/Write`
181			`--`
182			`s_stop_a, -- Stop condition generating`
183			`s_stop_b, -- Stop condition generating`
184			`s_stop_c, -- Stop condition generating`
185			`--`
186			`s_rstart_a, -- Preparation for Repeated Start`
187			`s_rstart_b, -- Preparation for Repeated Start`
188			`s_rstart_c -- Preparation for Repeated Start`
189			`);`
190
191			`------------------------------------------------------------------------------`
192			`-- Conversion from 'state_type' to 'std_logic_vector(3 downto 0)'`
193			`function to_std_logic_vector(a : state_type) return std_logic_vector is`
194			`begin`
195			`case (a) is`
196			`when s_idle => return "0000";`
197			`when s_start_a => return "0001";`
198			`when s_start_b => return "0010";`
199			`when s_start_c => return "0011";`
200			`when s_rw_a => return "0100";`
201			`when s_rw_b => return "0101";`
202			`when s_rw_c => return "0110";`
203			`when s_rw_d => return "0111";`
204			`when s_rw_e => return "1000";`
205			`when s_stop_a => return "1001";`
206			`when s_stop_b => return "1010";`
207			`when s_stop_c => return "1011";`
208			`when s_rstart_a => return "1100";`
209			`when s_rstart_b => return "1101";`
210			`when s_rstart_c => return "1110";`
211			`end case;`
212			`end function to_std_logic_vector;`
213			`------------------------------------------------------------------------------`
214
215			`signal state : state_type := s_idle; -- FSM state`
216			`signal cnt : integer range 0 to c_max_cnt := 0; -- Counter of clock cycles`
217			`signal d_reg : std_logic := '0'; -- Output data bit register`
218			`signal r_reg : std_logic := '0'; -- Read operation indication`
219			`signal i_reg : std_logic := '0'; -- Input data bit register`
220
221			`signal scl_cnt : integer range 0 to c_max_cnt := 0; -- Counter of cycles when scl is stable`
222
223			`-- Timing parameters:`
224			`signal max_cnt : integer range 0 to c_max_cnt := c_tp(0).max_cnt;`
225			`signal fe_cnt : integer range 0 to c_max_cnt := c_tp(0).fe_cnt;`
226			`signal t_hd_sta_cnt : integer range 0 to c_max_cnt := c_tp(0).t_hd_sta_cnt;`
227			`signal t_vd_dat_cnt : integer range 0 to c_max_cnt := c_tp(0).t_vd_dat_cnt;`
228			`signal t_high_cnt : integer range 0 to c_max_cnt := c_tp(0).t_high_cnt;`
229			`signal t_su_sto_cnt : integer range 0 to c_max_cnt := c_tp(0).t_su_sto_cnt;`
230			`signal t_su_sta_cnt : integer range 0 to c_max_cnt := c_tp(0).t_su_sta_cnt;`
231			`signal t_su_dat_cnt : integer range 0 to c_max_cnt := c_tp(0).t_su_dat_cnt;`
232
233			`begin`
234
235			`fsm_state <= to_std_logic_vector(state);`
236
237			`------------------------------------------------------------------------------`
238			`-- Changing timing parameters:`
239			`tp_proc:`
240			`process(clk)`
241			`begin`
242			`if rising_edge(clk) then`
243			`if (s_rst = '1') then`
244			`max_cnt <= c_tp(0).max_cnt;`
245			`fe_cnt <= c_tp(0).fe_cnt;`
246			`t_hd_sta_cnt <= c_tp(0).t_hd_sta_cnt;`
247			`t_vd_dat_cnt <= c_tp(0).t_vd_dat_cnt;`
248			`t_high_cnt <= c_tp(0).t_high_cnt;`
249			`t_su_sto_cnt <= c_tp(0).t_su_sto_cnt;`
250			`t_su_sta_cnt <= c_tp(0).t_su_sta_cnt;`
251			`t_su_dat_cnt <= c_tp(0).t_su_dat_cnt;`
252			`else`
253			`max_cnt <= c_tp(bus_id).max_cnt;`
254			`fe_cnt <= c_tp(bus_id).fe_cnt;`
255			`t_hd_sta_cnt <= c_tp(bus_id).t_hd_sta_cnt;`
256			`t_vd_dat_cnt <= c_tp(bus_id).t_vd_dat_cnt;`
257			`t_high_cnt <= c_tp(bus_id).t_high_cnt;`
258			`t_su_sto_cnt <= c_tp(bus_id).t_su_sto_cnt;`
259			`t_su_sta_cnt <= c_tp(bus_id).t_su_sta_cnt;`
260			`t_su_dat_cnt <= c_tp(bus_id).t_su_dat_cnt;`
261			`end if;`
262			`end if;`
263			`end process tp_proc;`
264			`------------------------------------------------------------------------------`
265
266			`------------------------------------------------------------------------------`
267			`-- Counting how long 'scl_i' input remains stable`
268			`scl_cnt_proc:`
269			`process(clk)`
270			`begin`
271			`if rising_edge(clk) then`
272			`if (s_rst = '1') then`
273			`scl_cnt <= 0;`
274			`else`
275			`if (scl_i_d /= scl_i) then`
276			`scl_cnt <= 1;`
277			`elsif (scl_cnt < max_cnt) then`
278			`scl_cnt <= scl_cnt + 1;`
279			`else`
280			`scl_cnt <= max_cnt;`
281			`end if;`
282			`end if;`
283			`end if;`
284			`end process scl_cnt_proc;`
285			`------------------------------------------------------------------------------`
286
287			`------------------------------------------------------------------------------`
288			`-- Main Finite State Machine:`
289			`process(clk)`
290			`begin`
291			`if rising_edge(clk) then`
292			`if (s_rst = '1') then`
293			`state <= s_idle;`
294			`d_reg <= '0';`
295			`i_reg <= '0';`
296			`r_reg <= '0';`
297			`cnt <= 0;`
298			`mbr_wr <= '0';`
299			`mbr <= mbr_done;`
300			`else`
301			`-- Defaults:`
302			`if (cnt < max_cnt) then`
303			`cnt <= cnt + 1;`
304			`else`
305			`cnt <= max_cnt;`
306			`end if;`
307			`mbr_wr <= '0';`
308			`------`
309
310			`case state is`
311			`-- 'Idle' state ----------------------------------`
312			`when s_idle =>`
313			`if (mbc_wr = '1') then`
314			`case (mbc) is`
315			`when mbc_start =>`
316			`state <= s_start_a;`
317			`when mbc_stop =>`
318			`assert false report "Stop command without Start command!" severity error;`
319			`mbr_wr <= '1';`
320			`mbr <= mbr_done;`
321			`when others =>`
322			`assert false report "In 'Idle' state only Start command allowed!" severity error;`
323			`mbr_wr <= '1';`
324			`mbr <= mbr_error;`
325			`end case;`
326			`cnt <= 0;`
327			`end if;`
328			`-- 'Idle' state ----------------------------------`
329
330			`-- 'Start A' state -------------------------------`
331			`when s_start_a =>`
332			`if (scl_i = '0')or(cnt = t_hd_sta_cnt) then -- t_{HD;STA} >= 4.0 us`
333			`state <= s_start_b;`
334			`end if;`
335			`-- 'Start A' state -------------------------------`
336
337			`-- 'Start B' state -------------------------------`
338			`when s_start_b =>`
339			`if (scl_i_d = '0')and(scl_cnt > t_vd_dat_cnt) then -- t_{VD;DAT} <= 3.45 us, t_{HD;DAT} >= 0 us;`
340			`state <= s_start_c;`
341			`mbr_wr <= '1';`
342			`mbr <= mbr_done;`
343			`end if;`
344			`-- 'Start B' state -------------------------------`
345
346			`-- 'Start C' state -------------------------------`
347			`when s_start_c =>`
348			`if (mbc_wr = '1') then`
349			`case (mbc) is`
350			`when mbc_write_0 =>`
351			`state <= s_rw_a;`
352			`d_reg <= '0'; -- data`
353			`r_reg <= '0'; -- read indication`
354			`when mbc_write_1 =>`
355			`state <= s_rw_a;`
356			`d_reg <= '1'; -- data`
357			`r_reg <= '0'; -- read indication`
358			`when mbc_read =>`
359			`state <= s_rw_a;`
360			`d_reg <= '1'; -- data`
361			`r_reg <= '1'; -- read indication`
362			`when mbc_stop =>`
363			`state <= s_stop_a;`
364			`when mbc_start =>`
365			`-- Second 'Start' command coming immediately after the first`
366			`-- one is ignored without an 'Error' response.`
367			`assert false report "Second Start command!" severity error;`
368			`mbr_wr <= '1';`
369			`mbr <= mbr_done;`
370			`end case;`
371			`cnt <= 0;`
372			`end if;`
373			`-- 'Start C' state -------------------------------`
374
375			`-- 'Read/Write A' state --------------------------`
376			`when s_rw_a =>`
377			`if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us`
378			`state <= s_rw_b;`
379			`end if;`
380			`-- 'Read/Write A' state --------------------------`
381
382			`-- 'Read/Write B' state --------------------------`
383			`when s_rw_b =>`
384			`if (scl_i = '1') then`
385			`state <= s_rw_c;`
386			`end if;`
387			`-- 'Read/Write B' state --------------------------`
388
389			`-- 'Read/Write C' state --------------------------`
390			`when s_rw_c =>`
391			`if (scl_i = '0')or((scl_cnt > t_high_cnt)and(cnt >= fe_cnt)) then -- t_{HIGH} >= 4.0 us;`
392			`state <= s_rw_d;`
393			`i_reg <= sda_i;`
394			`end if;`
395			`if (scl_i = '1')and(r_reg = '0')and(sda_i /= d_reg) then`
396			`mbr_wr <= '1';`
397			`mbr <= mbr_arb_lost; -- Arbitration lost`
398			`state <= s_idle;`
399			`end if;`
400			`-- 'Read/Write C' state --------------------------`
401
402			`-- 'Read/Write D' state --------------------------`
403			`when s_rw_d =>`
404			`if (scl_i_d = '0')and(scl_cnt > t_vd_dat_cnt)and(cnt = max_cnt) then -- t_{VD;DAT} <= 3.45 us, t_{HD;DAT} >= 0 us;`
405			`state <= s_rw_e;`
406			`mbr_wr <= '1';`
407			`if (r_reg = '0') then`
408			`mbr <= mbr_done; -- Successfull write`
409			`else`
410			`if (i_reg = '0') then`
411			`mbr <= mbr_bit_0; -- Bit 0 received`
412			`else`
413			`mbr <= mbr_bit_1; -- Bit 1 received`
414			`end if;`
415			`end if;`
416			`end if;`
417			`-- 'Read/Write D' state --------------------------`
418
419			`-- 'Read/Write E' state --------------------------`
420			`when s_rw_e =>`
421			`if (mbc_wr = '1') then`
422			`case (mbc) is`
423			`when mbc_write_0 =>`
424			`state <= s_rw_a;`
425			`d_reg <= '0'; -- data`
426			`r_reg <= '0'; -- read indication`
427			`when mbc_write_1 =>`
428			`state <= s_rw_a;`
429			`d_reg <= '1'; -- data`
430			`r_reg <= '0'; -- read indication`
431			`when mbc_read =>`
432			`state <= s_rw_a;`
433			`d_reg <= '1'; -- data`
434			`r_reg <= '1'; -- read indication`
435			`when mbc_start =>`
436			`state <= s_rstart_a;`
437			`when mbc_stop =>`
438			`state <= s_stop_a;`
439			`end case;`
440			`cnt <= 0;`
441			`end if;`
442			`-- 'Read/Write E' state --------------------------`
443
444			`-- 'Stop A' state --------------------------------`
445			`when s_stop_a =>`
446			`if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us`
447			`state <= s_stop_b;`
448			`end if;`
449			`-- 'Stop A' state --------------------------------`
450
451			`-- 'Stop B' state --------------------------------`
452			`when s_stop_b =>`
453			`if (scl_i = '1') then`
454			`state <= s_stop_c;`
455			`cnt <= 0;`
456			`end if;`
457			`-- 'Stop B' state --------------------------------`
458
459			`-- 'Stop C' state --------------------------------`
460			`when s_stop_c =>`
461			`if (cnt > t_su_sto_cnt) then -- t_{SU;STO} >= 4.0 us`
462			`state <= s_idle;`
463			`mbr_wr <= '1';`
464			`mbr <= mbr_done;`
465			`cnt <= 0;`
466			`end if;`
467			`-- 'Stop C' state --------------------------------`
468
469			`-- 'Repeated Start A' state ----------------------`
470			`when s_rstart_a =>`
471			`if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us`
472			`state <= s_rstart_b;`
473			`end if;`
474			`-- 'Repeated Start A' state ----------------------`
475
476			`-- 'Repeated Start B' state ----------------------`
477			`when s_rstart_b =>`
478			`if (scl_i = '1') then`
479			`state <= s_rstart_c;`
480			`end if;`
481			`-- 'Repeated Start B' state ----------------------`
482
483			`-- 'Repeated Start C' state ----------------------`
484			`when s_rstart_c =>`
485			`if (scl_i_d = '0')or((scl_cnt > t_su_sta_cnt)and(cnt = max_cnt)) then -- t_{SU;STA} >= 4.7 us`
486			`state <= s_start_a;`
487			`cnt <= 0;`
488			`end if;`
489			`if (scl_i = '1')and(sda_i = '0') then`
490			`mbr_wr <= '1';`
491			`mbr <= mbr_arb_lost; -- Arbitration lost`
492			`state <= s_idle;`
493			`end if;`
494			`-- 'Repeated Start C' state ----------------------`
495			`end case;`
496			`end if;`
497			`end if;`
498			`end process;`
499			`------------------------------------------------------------------------------`
500
501			`------------------------------------------------------------------------------`
502			`scl_sda_proc:`
503			`process(clk)`
504			`begin`
505			`if rising_edge(clk) then`
506			`if (s_rst = '1') then`
507			`scl_o <= '1';`
508			`sda_o <= '1';`
509			`else`
510			`case state is`
511			`when s_idle => sda_o <= '1'; scl_o <= '1';`
512			`when s_start_a => sda_o <= '0'; scl_o <= '1';`
513			`when s_start_b => sda_o <= '0'; scl_o <= '0';`
514			`when s_start_c => sda_o <= '0'; scl_o <= '0';`
515			`when s_rw_a => sda_o <= d_reg; scl_o <= '0';`
516			`when s_rw_b => sda_o <= d_reg; scl_o <= '1';`
517			`when s_rw_c => sda_o <= d_reg; scl_o <= '1';`
518			`when s_rw_d => sda_o <= d_reg; scl_o <= '0';`
519			`when s_rw_e => sda_o <= d_reg; scl_o <= '0';`
520			`when s_stop_a => sda_o <= '0'; scl_o <= '0';`
521			`when s_stop_b => sda_o <= '0'; scl_o <= '1';`
522			`when s_stop_c => sda_o <= '0'; scl_o <= '1';`
523			`when s_rstart_a => sda_o <= '1'; scl_o <= '0';`
524			`when s_rstart_b => sda_o <= '1'; scl_o <= '1';`
525			`when s_rstart_c => sda_o <= '1'; scl_o <= '1';`
526			`end case;`
527			`end if;`
528			`end if;`
529			`end process scl_sda_proc;`
530			`------------------------------------------------------------------------------`
531
532			`end architecture rtl;`
533			`--==============================================================================`
534