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sshuv2 |
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--==============================================================================
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-- |
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-- Project: IIC Multiple Bus Controller (IICMB) |
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-- |
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-- Module: Command sequencer for 'iicmb_m'. |
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-- Version: |
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-- 1.0, April 29, 2016 |
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-- |
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-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) |
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-- |
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--==============================================================================
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--==============================================================================
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-- Copyright (c) 2016, Sergey Shuvalkin |
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-- All rights reserved. |
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-- |
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-- Redistribution and use in source and binary forms, with or without |
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-- modification, are permitted provided that the following conditions are met: |
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-- |
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-- 1. Redistributions of source code must retain the above copyright notice, |
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-- this list of conditions and the following disclaimer. |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- notice, this list of conditions and the following disclaimer in the |
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-- documentation and/or other materials provided with the distribution. |
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-- |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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-- POSSIBILITY OF SUCH DAMAGE. |
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--==============================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use work.iicmb_pkg.all;
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--==============================================================================
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entity sequencer is
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generic
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(
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g_cmd : seq_cmd_type_array := c_empty_array -- Sequence of commands (supported: WAIT, SET_BUS and WRITE_BYTE)
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);
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port
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(
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------------------------------------
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clk : in std_logic; -- Clock input
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s_rst : in std_logic; -- Synchronous reset (active high)
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------------------------------------
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------------------------------------
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cs_start : in std_logic; -- Start executing command sequence
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cs_busy : out std_logic; -- Command sequence is being executed
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cs_status : out std_logic_vector(2 downto 0); -- Execution status
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------------------------------------
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------------------------------------
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-- Status:
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busy : in std_logic; -- Bus busy status
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captured : in std_logic; -- Bus captured status
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bus_id : in std_logic_vector(3 downto 0); -- ID of selected I2C bus
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bit_state : in std_logic_vector(3 downto 0); -- State of bit level FSM
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byte_state : in std_logic_vector(3 downto 0); -- State of byte level FSM
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------------------------------------
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------------------------------------
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-- 'Generic interface' signals:
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mcmd_wr : out std_logic; -- Byte command write (active high)
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mcmd_id : out std_logic_vector(2 downto 0); -- Byte command ID
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mcmd_data : out std_logic_vector(7 downto 0); -- Command data
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--
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mrsp_wr : in std_logic; -- Byte response write (active high)
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mrsp_id : in std_logic_vector(2 downto 0); -- Byte response ID
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mrsp_data : in std_logic_vector(7 downto 0) -- Response data
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------------------------------------
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);
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end entity sequencer;
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--==============================================================================
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--==============================================================================
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architecture rtl of sequencer is
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type cmd_type_array is array (natural range <>) of std_logic_vector(10 downto 0);
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------------------------------------------------------------------------------
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function get_cmd_seq_length(a : seq_cmd_type_array) return natural is
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variable v_ret : natural := 0;
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begin
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for i in a'range loop
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case a(i).id is
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when seq_wait => v_ret := v_ret + 1;
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when seq_set_bus => v_ret := v_ret + 1;
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when seq_write_byte => v_ret := v_ret + 5;
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end case;
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end loop;
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return v_ret;
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end function get_cmd_seq_length;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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function get_cmd_seq(a : seq_cmd_type_array) return cmd_type_array is
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variable v_ret : cmd_type_array(0 to (get_cmd_seq_length(a) - 1));
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variable j : integer;
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begin
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j := 0;
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for i in a'range loop
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case a(i).id is
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when seq_wait =>
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v_ret(j) := mcmd_wait & a(i).data;
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j := j + 1;
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when seq_set_bus =>
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v_ret(j) := mcmd_set_bus & a(i).data;
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j := j + 1;
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when seq_write_byte =>
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v_ret(j + 0) := mcmd_start & x"00";
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v_ret(j + 1) := mcmd_write & a(i).saddr & "0";
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v_ret(j + 2) := mcmd_write & a(i).daddr;
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v_ret(j + 3) := mcmd_write & a(i).data;
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v_ret(j + 4) := mcmd_stop & x"00";
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j := j + 5;
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end case;
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end loop;
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return v_ret;
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end function get_cmd_seq;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Sequence of commands to execute:
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constant cmd_seq : cmd_type_array := get_cmd_seq(g_cmd);
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------------------------------------------------------------------------------
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type state_type is (s_idle, s_active);
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signal state : state_type := s_idle;
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signal cmd_cnt : integer range 0 to cmd_seq'length := 0;
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begin
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------------------------------------------------------------------------------
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state_proc:
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process(clk)
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begin
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if rising_edge(clk) then
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if (s_rst = '1') then
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state <= s_idle;
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cmd_cnt <= 0;
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cs_busy <= '0';
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cs_status <= mrsp_done;
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mcmd_wr <= '0';
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mcmd_id <= "000";
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mcmd_data <= "00000000";
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else
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-- Defaults:
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mcmd_wr <= '0';
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-- FSM:
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case state is
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-------------- 's_idle' state ------------------------
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when s_idle =>
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cs_busy <= '0';
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if (cs_start = '1') then
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if (cmd_cnt = cmd_seq'length) then
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cs_status <= mrsp_done;
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cmd_cnt <= 0;
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else
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state <= s_active;
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cmd_cnt <= cmd_cnt + 1;
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cs_busy <= '1';
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mcmd_wr <= '1';
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mcmd_id <= cmd_seq(cmd_cnt)(10 downto 8);
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mcmd_data <= cmd_seq(cmd_cnt)( 7 downto 0);
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end if;
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end if;
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-------------- 's_idle' state ------------------------
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-------------- 's_active' state ----------------------
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when s_active =>
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cs_busy <= '1';
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if (mrsp_wr = '1') then
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case mrsp_id is
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when mrsp_nak | mrsp_arb_lost | mrsp_error =>
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state <= s_idle;
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cmd_cnt <= 0;
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cs_busy <= '0';
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cs_status <= mrsp_id;
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when others =>
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if (cmd_cnt = cmd_seq'length) then
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state <= s_idle;
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cmd_cnt <= 0;
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cs_busy <= '0';
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cs_status <= mrsp_done;
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else
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cmd_cnt <= cmd_cnt + 1;
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mcmd_wr <= '1';
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mcmd_id <= cmd_seq(cmd_cnt)(10 downto 8);
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mcmd_data <= cmd_seq(cmd_cnt)( 7 downto 0);
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end if;
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end case;
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end if;
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-------------- 's_active' state ----------------------
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end case;
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end if;
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end if;
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end process state_proc;
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------------------------------------------------------------------------------
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end architecture rtl;
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--==============================================================================
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