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sshuv2 |
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--==============================================================================
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-- |
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-- Project: IIC Multiple Bus Controller (IICMB) |
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-- |
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-- Module: Testbench for 'iicmb_m_wb'. |
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-- Version: |
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-- 1.0, April 29, 2016 |
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sshuv2 |
-- 1.1, May 10, 2016 Changed i2c_slave_model instance |
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-- parameter interface |
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sshuv2 |
-- |
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-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) |
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-- |
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--==============================================================================
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--==============================================================================
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-- Copyright (c) 2016, Sergey Shuvalkin |
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-- All rights reserved. |
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-- |
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-- Redistribution and use in source and binary forms, with or without |
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-- modification, are permitted provided that the following conditions are met: |
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-- |
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-- 1. Redistributions of source code must retain the above copyright notice, |
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-- this list of conditions and the following disclaimer. |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- notice, this list of conditions and the following disclaimer in the |
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-- documentation and/or other materials provided with the distribution. |
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-- |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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-- POSSIBILITY OF SUCH DAMAGE. |
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--==============================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library iicmb;
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use iicmb.iicmb_pkg.all;
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use work.test.all;
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--==============================================================================
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entity iicmb_m_wb_tb is
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end entity iicmb_m_wb_tb;
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--==============================================================================
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--==============================================================================
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architecture beh of iicmb_m_wb_tb is
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constant c_f_clk : real := 100000.0; -- in kHz
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constant c_f_scl_0 : real := 100.0; -- in kHz
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constant c_f_scl_1 : real := 100.0; -- in kHz
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constant c_f_scl_2 : real := 100.0; -- in kHz
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constant c_f_scl_3 : real := 100.0; -- in kHz
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constant c_p_clk : time := integer(1000000000.0/c_f_clk) * 1 ps;
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constant c_bus_num : positive := 4;
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------------------------------------------------------------------------------
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component iicmb_m_wb is
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generic
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(
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g_bus_num : positive range 1 to 16 := 1;
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g_f_clk : real := 100000.0;
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g_f_scl_0 : real := 100.0;
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g_f_scl_1 : real := 100.0;
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g_f_scl_2 : real := 100.0;
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g_f_scl_3 : real := 100.0;
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g_f_scl_4 : real := 100.0;
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g_f_scl_5 : real := 100.0;
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g_f_scl_6 : real := 100.0;
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g_f_scl_7 : real := 100.0;
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g_f_scl_8 : real := 100.0;
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g_f_scl_9 : real := 100.0;
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g_f_scl_a : real := 100.0;
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g_f_scl_b : real := 100.0;
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g_f_scl_c : real := 100.0;
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g_f_scl_d : real := 100.0;
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g_f_scl_e : real := 100.0;
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g_f_scl_f : real := 100.0
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);
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port
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(
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clk_i : in std_logic;
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rst_i : in std_logic;
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cyc_i : in std_logic;
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stb_i : in std_logic;
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ack_o : out std_logic;
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adr_i : in std_logic_vector(1 downto 0);
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we_i : in std_logic;
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dat_i : in std_logic_vector(7 downto 0);
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dat_o : out std_logic_vector(7 downto 0);
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irq : out std_logic;
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scl_i : in std_logic_vector(0 to g_bus_num - 1);
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sda_i : in std_logic_vector(0 to g_bus_num - 1);
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scl_o : out std_logic_vector(0 to g_bus_num - 1);
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sda_o : out std_logic_vector(0 to g_bus_num - 1)
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);
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end component iicmb_m_wb;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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component wire_mdl is
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generic
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(
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g_resistance_0 : real := 1.0; -- In Ohms
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g_resistance_1 : real := 1.0; -- In Ohms
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g_capacitance : real := 1.0; -- In pF
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g_initial_level : bit := '0'
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);
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port
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(
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sig_in : in bit;
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sig_out : out real;
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sig_out_l : out bit
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);
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end component wire_mdl;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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component i2c_slave_model is
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generic
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(
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4 |
sshuv2 |
I2C_ADR : integer
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2 |
sshuv2 |
);
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port
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(
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scl : inout std_logic;
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sda : inout std_logic
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);
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end component i2c_slave_model;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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function get_slave_addr(n : natural) return std_logic_vector is
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variable ret : std_logic_vector(6 downto 0);
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begin
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ret := "010" & std_logic_vector(to_unsigned(n, 4));
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return ret;
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end function get_slave_addr;
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------------------------------------------------------------------------------
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signal clk_i : std_logic := '0';
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signal rst_i : std_logic := '1';
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signal cyc_i : std_logic := '0';
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signal stb_i : std_logic := '0';
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signal ack_o : std_logic;
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signal adr_i : std_logic_vector(1 downto 0) := "00";
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signal we_i : std_logic := '0';
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signal dat_i : std_logic_vector(7 downto 0) := "00000000";
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signal dat_o : std_logic_vector(7 downto 0);
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signal scl_o : std_logic_vector(0 to c_bus_num - 1) := (others => '1');
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signal scl : std_logic_vector(0 to c_bus_num - 1) := (others => 'H');
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signal sda_o : std_logic_vector(0 to c_bus_num - 1) := (others => '1');
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signal sda : std_logic_vector(0 to c_bus_num - 1) := (others => 'H');
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type real_vector is array (natural range <>) of real;
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signal scl_real : real_vector(0 to c_bus_num - 1);
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signal sda_real : real_vector(0 to c_bus_num - 1);
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signal scl_quant : bit_vector(0 to c_bus_num - 1);
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signal sda_quant : bit_vector(0 to c_bus_num - 1);
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signal scl_nquant : bit_vector(0 to c_bus_num - 1) := (others => '1');
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signal sda_nquant : bit_vector(0 to c_bus_num - 1) := (others => '1');
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signal irq : std_logic;
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---- Byte-wide commands:
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constant wb_m_set_bus : std_logic_vector(7 downto 0) := "00000" & mcmd_set_bus;
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constant wb_m_write : std_logic_vector(7 downto 0) := "00000" & mcmd_write;
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constant wb_m_read_ack : std_logic_vector(7 downto 0) := "00000" & mcmd_read_ack;
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constant wb_m_read_nak : std_logic_vector(7 downto 0) := "00000" & mcmd_read_nak;
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constant wb_m_start : std_logic_vector(7 downto 0) := "00000" & mcmd_start;
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constant wb_m_stop : std_logic_vector(7 downto 0) := "00000" & mcmd_stop;
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constant wb_m_wait : std_logic_vector(7 downto 0) := "00000" & mcmd_wait;
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begin
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clk_i <= not(clk_i) after c_p_clk / 2;
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rst_i <= '1', '0' after 113 ns;
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------------------------------------------------------------------------------
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-- Wishbone bus activity process:
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process
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----------------------------------------------------------------------------
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procedure wb_write(addr : in std_logic_vector(1 downto 0); data : in std_logic_vector(7 downto 0)) is
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begin
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cyc_i <= '1';
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stb_i <= '1';
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adr_i <= addr;
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we_i <= '1';
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dat_i <= data;
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wait until rising_edge(clk_i)and(ack_o = '1');
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cyc_i <= '0';
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stb_i <= '0';
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print_string("Wishbone Write: 0x" & to_string(addr, "X", 2) & " : " & "0x" & to_string(data, "X", 2) & newline);
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end procedure wb_write;
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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procedure wb_read(addr : in std_logic_vector(1 downto 0); data : out std_logic_vector(7 downto 0)) is
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begin
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cyc_i <= '1';
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stb_i <= '1';
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adr_i <= addr;
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we_i <= '0';
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wait until rising_edge(clk_i)and(ack_o = '1');
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data := dat_o;
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cyc_i <= '0';
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stb_i <= '0';
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print_string("Wishbone Read : 0x" & to_string(addr, "X", 2) & " : " & "0x" & to_string(dat_o, "X", 2) & newline);
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end procedure wb_read;
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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procedure wb_wait(n : in positive) is
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begin
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print_string("Wishbone Waiting for " & integer'image(n) & " cycles." & newline);
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cyc_i <= '0';
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stb_i <= '0';
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for i in 0 to n - 1 loop
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wait until rising_edge(clk_i);
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end loop;
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end procedure wb_wait;
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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procedure wb_halt is
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begin
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print_string("Wishbone Halted" & newline);
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cyc_i <= '0';
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stb_i <= '0';
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wait;
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end procedure wb_halt;
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----------------------------------------------------------------------------
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procedure i2c_write_byte(slave_addr : in std_logic_vector(6 downto 0); addr : in std_logic_vector(7 downto 0); data : in std_logic_vector(7 downto 0)) is
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variable v_tmp : std_logic_vector(7 downto 0);
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begin
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wb_write("10", wb_m_start);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("01", slave_addr & "0");
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wb_write("10", wb_m_write);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("01", addr);
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wb_write("10", wb_m_write);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("01", data);
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wb_write("10", wb_m_write);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("10", wb_m_stop);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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end procedure i2c_write_byte;
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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procedure i2c_read_byte(slave_addr : in std_logic_vector(6 downto 0); addr : in std_logic_vector(7 downto 0); data : out std_logic_vector(7 downto 0)) is
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variable v_tmp : std_logic_vector(7 downto 0);
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begin
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wb_write("10", wb_m_start);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("01", slave_addr & "0");
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wb_write("10", wb_m_write);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("01", addr);
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wb_write("10", wb_m_write);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("10", wb_m_start);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("01", slave_addr & "1");
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wb_write("10", wb_m_write);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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--
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wb_write("10", wb_m_read_nak);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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wb_read("01", data);
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--
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wb_write("10", wb_m_stop);
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wait until rising_edge(clk_i)and(irq = '1');
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wb_read("10", v_tmp);
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assert (v_tmp(7) = '1') report "Something gone wrong" severity error;
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end procedure i2c_read_byte;
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317 |
|
|
----------------------------------------------------------------------------
|
318 |
|
|
variable v_data : std_logic_vector(7 downto 0);
|
319 |
|
|
begin
|
320 |
|
|
-- Initial delay:
|
321 |
|
|
wb_wait(100);
|
322 |
|
|
|
323 |
|
|
--
|
324 |
|
|
wb_read("00", v_data);
|
325 |
|
|
wb_read("01", v_data);
|
326 |
|
|
wb_read("10", v_data);
|
327 |
|
|
wb_wait(1);
|
328 |
|
|
wb_read("11", v_data);
|
329 |
|
|
--
|
330 |
|
|
wb_wait(10);
|
331 |
|
|
-- Enable controller and interrupts
|
332 |
|
|
wb_write("00", "11000000");
|
333 |
|
|
wb_read("00", v_data);
|
334 |
|
|
--
|
335 |
|
|
-- Select Bus #1
|
336 |
|
|
wb_wait(10);
|
337 |
|
|
wb_write("01", "00000001");
|
338 |
|
|
wb_write("10", wb_m_set_bus);
|
339 |
|
|
wb_wait(1);
|
340 |
|
|
wb_read("10", v_data);
|
341 |
|
|
--
|
342 |
|
|
|
343 |
|
|
--
|
344 |
|
|
wb_wait(10);
|
345 |
|
|
i2c_write_byte(get_slave_addr(1), x"00", x"4A");
|
346 |
|
|
i2c_write_byte(get_slave_addr(1), x"01", x"67");
|
347 |
|
|
--
|
348 |
|
|
|
349 |
|
|
--
|
350 |
|
|
wb_wait(10);
|
351 |
|
|
i2c_read_byte(get_slave_addr(1), x"00", v_data);
|
352 |
|
|
print_string("Data read: " & to_string(v_data, "X", 2) & newline);
|
353 |
|
|
i2c_read_byte(get_slave_addr(1), x"01", v_data);
|
354 |
|
|
print_string("Data read: " & to_string(v_data, "X", 2) & newline);
|
355 |
|
|
--
|
356 |
|
|
|
357 |
|
|
-- Halt bus activity
|
358 |
|
|
wb_halt;
|
359 |
|
|
end process;
|
360 |
|
|
------------------------------------------------------------------------------
|
361 |
|
|
|
362 |
|
|
------------------------------------------------------------------------------
|
363 |
|
|
dut : iicmb_m_wb
|
364 |
|
|
generic map
|
365 |
|
|
(
|
366 |
|
|
g_bus_num => c_bus_num,
|
367 |
|
|
g_f_clk => c_f_clk,
|
368 |
|
|
g_f_scl_0 => c_f_scl_0,
|
369 |
|
|
g_f_scl_1 => c_f_scl_1,
|
370 |
|
|
g_f_scl_2 => c_f_scl_2,
|
371 |
|
|
g_f_scl_3 => c_f_scl_3
|
372 |
|
|
)
|
373 |
|
|
port map
|
374 |
|
|
(
|
375 |
|
|
clk_i => clk_i,
|
376 |
|
|
rst_i => rst_i,
|
377 |
|
|
cyc_i => cyc_i,
|
378 |
|
|
stb_i => stb_i,
|
379 |
|
|
ack_o => ack_o,
|
380 |
|
|
adr_i => adr_i,
|
381 |
|
|
we_i => we_i,
|
382 |
|
|
dat_i => dat_i,
|
383 |
|
|
dat_o => dat_o,
|
384 |
|
|
irq => irq,
|
385 |
|
|
scl_i => to_stdlogicvector(scl_quant),
|
386 |
|
|
sda_i => to_stdlogicvector(sda_quant),
|
387 |
|
|
scl_o => scl_o,
|
388 |
|
|
sda_o => sda_o
|
389 |
|
|
);
|
390 |
|
|
------------------------------------------------------------------------------
|
391 |
|
|
|
392 |
|
|
--****************************************************************************
|
393 |
|
|
bus_gen:
|
394 |
|
|
for i in 0 to c_bus_num - 1 generate
|
395 |
|
|
scl(i) <= '0' when (scl_o(i) = '0') else 'Z';
|
396 |
|
|
sda(i) <= '0' when (sda_o(i) = '0') else 'Z';
|
397 |
|
|
|
398 |
|
|
----------------------------------------------------------------------------
|
399 |
|
|
wire_mdl_inst_0 : wire_mdl
|
400 |
|
|
generic map
|
401 |
|
|
(
|
402 |
|
|
g_resistance_0 => 40.0,
|
403 |
|
|
g_resistance_1 => 4000.0,
|
404 |
|
|
g_capacitance => 200.0, -- In pF
|
405 |
|
|
g_initial_level => '1'
|
406 |
|
|
)
|
407 |
|
|
port map
|
408 |
|
|
(
|
409 |
|
|
sig_in => scl_nquant(i),
|
410 |
|
|
sig_out => scl_real(i),
|
411 |
|
|
sig_out_l => scl_quant(i)
|
412 |
|
|
);
|
413 |
|
|
----------------------------------------------------------------------------
|
414 |
|
|
|
415 |
|
|
----------------------------------------------------------------------------
|
416 |
|
|
wire_mdl_inst_1 : wire_mdl
|
417 |
|
|
generic map
|
418 |
|
|
(
|
419 |
|
|
g_resistance_0 => 40.0,
|
420 |
|
|
g_resistance_1 => 4000.0,
|
421 |
|
|
g_capacitance => 200.0, -- In pF
|
422 |
|
|
g_initial_level => '1'
|
423 |
|
|
)
|
424 |
|
|
port map
|
425 |
|
|
(
|
426 |
|
|
sig_in => sda_nquant(i),
|
427 |
|
|
sig_out => sda_real(i),
|
428 |
|
|
sig_out_l => sda_quant(i)
|
429 |
|
|
);
|
430 |
|
|
----------------------------------------------------------------------------
|
431 |
|
|
|
432 |
|
|
----------------------------------------------------------------------------
|
433 |
|
|
i2c_slave_model_inst0 : i2c_slave_model
|
434 |
|
|
generic map
|
435 |
|
|
(
|
436 |
4 |
sshuv2 |
I2C_ADR => to_integer(unsigned(get_slave_addr(i)))
|
437 |
2 |
sshuv2 |
)
|
438 |
|
|
port map
|
439 |
|
|
(
|
440 |
|
|
scl => scl(i),
|
441 |
|
|
sda => sda(i)
|
442 |
|
|
);
|
443 |
|
|
----------------------------------------------------------------------------
|
444 |
|
|
end generate bus_gen;
|
445 |
|
|
--****************************************************************************
|
446 |
|
|
|
447 |
|
|
scl <= (others => 'H'); -- Pull up
|
448 |
|
|
sda <= (others => 'H'); -- Pull up
|
449 |
|
|
|
450 |
|
|
scl_nquant <= to_bitvector(to_x01(scl));
|
451 |
|
|
sda_nquant <= to_bitvector(to_x01(sda));
|
452 |
|
|
|
453 |
|
|
end architecture beh;
|
454 |
|
|
--==============================================================================
|
455 |
|
|
|