OpenCores
URL https://opencores.org/ocsvn/ima_adpcm_enc_dec/ima_adpcm_enc_dec/trunk

Subversion Repositories ima_adpcm_enc_dec

[/] [ima_adpcm_enc_dec/] [trunk/] [scilab/] [test_ima_adpcm.sce] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 motilito
// this script tests the ADC encoder & decoder
2
mode(-1)
3
 
4
// set script parameters
5
// set to non zero to enable user selected WAV file
6
select_file_gui = 1;
7
// set default file name when GUI is disabled or canceled
8
default_filename = "1234.wav";
9
// maximum length of audio samples to limit the runtime & verilog vector files
10
// set to 0 to disable any size limiting
11
maximum_samp_len = 0;
12
// set to non zero value to enable verilog simulation input & output vectors creation
13
verilog_vec_enable = 0;
14
 
15
// get the functions
16
getd();
17
 
18
// set name of input WAV file
19
if (select_file_gui),
20
        // get file from the user
21
        fname=uigetfile("*.wav", "", "Select WAV File");
22
        // check if default file should be used
23
        if ~length(fname),
24
                fname = default_filename;
25
        end
26
else
27
        // use default filename
28
        fname = default_filename;
29
end
30
 
31
// load the WAV linear samples file
32
[samp, wav_Fs, wav_bits] = wavread(fname);
33
// only use a single channel
34
samp = samp(1, :);
35
// number of bits must be 16
36
if (wav_bits ~= 16),
37
        error("ERROR: WAV file must be 16 bits.");
38
end
39
 
40
// limit the length of the input samples vector
41
if (maximum_samp_len),
42
        samp = samp(1:min(maximum_samp_len, length(samp)));
43
end
44
 
45
// call the encoder
46
enc_samp = ima_adpcm_enc(samp);
47
 
48
// call the decoder
49
dec_samp = ima_adpcm_dec(enc_samp);
50
 
51
// sound the result
52
sound(dec_samp/max(abs(dec_samp)), wav_Fs);
53
 
54
// enable the following code to write Verilog simulation binary files
55
if (verilog_vec_enable),
56
        // save the input samples to a binary file used by the verilog simulation
57
        samp = round(samp * (2^15-1));
58
        fid = mopen("test_in.bin", "wb");
59
        mput(samp, "s");
60
        mclose(fid);
61
 
62
        // save the ADPCM encoded values
63
        fid = mopen("test_enc.bin", "wb");
64
        mput(enc_samp, "uc");
65
        mclose(fid);
66
 
67
        // before saving the decoder samples they should be rounded using the hardware
68
        // rounding implementation which only creates differences for negative .5
69
        // values.
70
//      round_dec_samp = round(dec_samp);
71
//      cor_idx = find((round_dec_samp - dec_samp) == -0.5);
72
//      round_dec_samp(cor_idx) = round_dec_samp(cor_idx) + 1;
73
        // save the decoded samples
74
        fid = mopen("test_dec.bin", "wb");
75
        mput(dec_samp, "s");
76
        mclose(fid);
77
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.