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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [accMUX.v] - Blame information for rev 3

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`include "timescale.v"
`include "defines.v"
 
 
module accumulatorMUX (accMuxSel, immData, aluOut, accMuxOut);
 
        input [`accMuxSelLen-1:0]        accMuxSel;
        input [`immDataLen-1:0]          immData;
        input   [7:0]    aluOut;
 
        output [7:0]     accMuxOut;
 
        reg [7:0]        accMuxOut;
 
 
        always @ *
        begin
 
                case (accMuxSel)
 
                        `accMuxSel0     :       begin
                                                                accMuxOut = immData;
                                                                end
 
                        `accMuxSel1     :       begin
                                                                accMuxOut = aluOut;
                                                                end
 
                        default         :       begin
                                                                accMuxOut = 8'bzzzzzzzz;
                                                                end
 
                endcase
 
        end
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6			`module accumulatorMUX (accMuxSel, immData, aluOut, accMuxOut);`
7
8			input [`accMuxSelLen-1:0] accMuxSel;
9			input [`immDataLen-1:0] immData;
10			`input [7:0] aluOut;`
11
12			`output [7:0] accMuxOut;`
13
14			`reg [7:0] accMuxOut;`
15
16
17			`always @ *`
18			`begin`
19
20			`case (accMuxSel)`
21
22			`accMuxSel0 : begin
23			`accMuxOut = immData;`
24			`end`
25
26			`accMuxSel1 : begin
27			`accMuxOut = aluOut;`
28			`end`
29
30			`default : begin`
31			`accMuxOut = 8'bzzzzzzzz;`
32			`end`
33
34			`endcase`
35
36			`end`
37
38
39			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [accMUX.v] - Blame information for rev 3