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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [accMUX.v] - Blame information for rev 5

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`include "timescale.v"
`include "defines.v"
 
 
module accumulatorMUX (accMuxSel, immData, aluOut
                                                                `ifdef timerAndCounter_peripheral
                                                                , tcLoadIn, tcAccIn
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartDataIn
                                                                `endif
                                                                `ifdef SPI_peripheral
                                                                , spiStatIn, spiBufIn
                                                                `endif
                                                                , accMuxOut
                                                                );
 
        input [`accMuxSelLen-1:0]        accMuxSel;
        input [`immDataLen-1:0]          immData;
        input   [7:0]    aluOut;
        `ifdef timerAndCounter_peripheral
        input [7:0] tcLoadIn, tcAccIn;
        `endif
        `ifdef UART_peripheral
        input [7:0] uartDataIn;
        `endif
        `ifdef SPI_peripheral
        input [7:0] spiStatIn, spiBufIn;
        `endif
 
        output [7:0]     accMuxOut;
 
        reg [7:0]        accMuxOut;
 
 
        always @ *
        begin
 
                case (accMuxSel)
 
                        `accMuxSelImmData       :       begin
                                                                                accMuxOut = immData;
                                                                                end
 
                        `accMuxSelAluOut        :       begin
                                                                                accMuxOut = aluOut;
                                                                                end
 
                        `ifdef timerAndCounter_peripheral
                        `accMuxSelTcLoad        :       begin
                                                                                accMuxOut = tcLoadIn;
                                                                                end
 
                        `accMuxSelTcAcc :       begin
                                                                                accMuxOut = tcAccIn;
                                                                                end
                        `endif
 
                        `ifdef UART_peripheral
                        `accMuxSelUart  :               begin
                                                                                accMuxOut = uartDataIn;
                                                                                end
                        `endif
 
                        `ifdef SPI_peripheral
                        `accMuxSelSpiStat       :       begin
                                                                                accMuxOut = spiStatIn;
                                                                                end
 
                        `accMuxSelSpiBuf        :       begin
                                                                                accMuxOut = spiBufIn;
                                                                                end
                        `endif
 
 
                        default         :       begin
                                                                accMuxOut = 8'bzzzzzzzz;
                                                                end
 
                endcase
 
        end
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6	5	maheshpalv	`module accumulatorMUX (accMuxSel, immData, aluOut`
7			`ifdef timerAndCounter_peripheral
8			`, tcLoadIn, tcAccIn`
9			`endif
10			`ifdef UART_peripheral
11			`, uartDataIn`
12			`endif
13			`ifdef SPI_peripheral
14			`, spiStatIn, spiBufIn`
15			`endif
16			`, accMuxOut`
17			`);`
18	3	maheshpalv
19			input [`accMuxSelLen-1:0] accMuxSel;
20			input [`immDataLen-1:0] immData;
21			`input [7:0] aluOut;`
22	5	maheshpalv	`ifdef timerAndCounter_peripheral
23			`input [7:0] tcLoadIn, tcAccIn;`
24			`endif
25			`ifdef UART_peripheral
26			`input [7:0] uartDataIn;`
27			`endif
28			`ifdef SPI_peripheral
29			`input [7:0] spiStatIn, spiBufIn;`
30			`endif
31	3	maheshpalv
32			`output [7:0] accMuxOut;`
33
34			`reg [7:0] accMuxOut;`
35
36
37			`always @ *`
38			`begin`
39
40			`case (accMuxSel)`
41
42	5	maheshpalv	`accMuxSelImmData : begin
43			`accMuxOut = immData;`
44			`end`
45	3	maheshpalv
46	5	maheshpalv	`accMuxSelAluOut : begin
47			`accMuxOut = aluOut;`
48			`end`
49	3	maheshpalv
50	5	maheshpalv	`ifdef timerAndCounter_peripheral
51			`accMuxSelTcLoad : begin
52			`accMuxOut = tcLoadIn;`
53			`end`
54
55			`accMuxSelTcAcc : begin
56			`accMuxOut = tcAccIn;`
57			`end`
58			`endif
59
60			`ifdef UART_peripheral
61			`accMuxSelUart : begin
62			`accMuxOut = uartDataIn;`
63			`end`
64			`endif
65
66			`ifdef SPI_peripheral
67			`accMuxSelSpiStat : begin
68			`accMuxOut = spiStatIn;`
69			`end`
70
71			`accMuxSelSpiBuf : begin
72			`accMuxOut = spiBufIn;`
73			`end`
74			`endif
75
76
77	3	maheshpalv	`default : begin`
78			`accMuxOut = 8'bzzzzzzzz;`
79			`end`
80
81			`endcase`
82
83			`end`
84
85
86			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [accMUX.v] - Blame information for rev 5