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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [alu.v] - Blame information for rev 10

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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
        module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn,
                                output [7:0] aluOut, output carryOut);
 
 
                wire [8:0] operand1 = {1'b0, op1};
                wire [8:0] operand2 = {1'b0, op2};
 
                wire [8:0] addRes = operand1 + operand2;
                wire [8:0] subRes = operand1 - operand2;
 
                reg [8:0] aluOut = 0;
                reg carryOut = 0;
 
                always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)
                begin
 
 
                if (aluEn)
                begin
 
                                case (aluOpcode)
 
                                `AND_alu        :       begin
                                                                aluOut = op1 & op2;
                                                                end
 
                                `OR_alu         :       begin
                                                                aluOut = op1 | op2;
                                                                end
 
                                `XOR_alu        :       begin
                                                                aluOut = op1^op2;
                                                                end
 
                                `GT_alu         :       begin
                                                                aluOut = op1>op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `GE_alu         :       begin
                                                                aluOut = op1>=op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `EQ_alu         :       begin
                                                                aluOut = op1==op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `LE_alu         :       begin
                                                                aluOut = op1<=op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `LT_alu         :       begin
                                                                aluOut = op1<op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `ADD_alu        :       begin
                                                                aluOut = addRes[7:0];
                                                                carryOut = addRes[8];
                                                                end
 
                                `SUB_alu        :       begin
                                                                aluOut = subRes[7:0];
                                                                carryOut = subRes[8];
                                                                end
 
                                `LD_data        :       begin
                                                                aluOut = op2;
                                                                end
 
                                default         :       begin
                                                                aluOut = 16'b0;
                                                                $write ("\nUnknown operation. \tmodule : ALU");
                                                                end
                                endcase
 
                        end
                        else
                        begin
 
                                aluOut = aluOut;
                        end
 
                end
 
endmodule

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40	3	maheshpalv
41			`include "timescale.v"
42			`include "defines.v"
43
44	6	maheshpalv	module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn,
45	3	maheshpalv	`output [7:0] aluOut, output carryOut);`
46
47
48			`wire [8:0] operand1 = {1'b0, op1};`
49			`wire [8:0] operand2 = {1'b0, op2};`
50
51			`wire [8:0] addRes = operand1 + operand2;`
52			`wire [8:0] subRes = operand1 - operand2;`
53
54	9	maheshpalv	`reg [8:0] aluOut = 0;`
55			`reg carryOut = 0;`
56	3	maheshpalv
57	7	maheshpalv	`always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)`
58	3	maheshpalv	`begin`
59
60
61	6	maheshpalv	`if (aluEn)`
62			`begin`
63
64			`case (aluOpcode)`
65
66			`AND_alu : begin
67	9	maheshpalv	`aluOut = op1 & op2;`
68	6	maheshpalv	`end`
69
70			`OR_alu : begin
71	9	maheshpalv	`aluOut = op1 \| op2;`
72	6	maheshpalv	`end`
73
74			`XOR_alu : begin
75	9	maheshpalv	`aluOut = op1^op2;`
76	6	maheshpalv	`end`
77
78			`GT_alu : begin
79	9	maheshpalv	`aluOut = op1>op2 ? 1'b1 : 1'b0;`
80	6	maheshpalv	`end`
81
82			`GE_alu : begin
83	9	maheshpalv	`aluOut = op1>=op2 ? 1'b1 : 1'b0;`
84	6	maheshpalv	`end`
85
86			`EQ_alu : begin
87	9	maheshpalv	`aluOut = op1==op2 ? 1'b1 : 1'b0;`
88	6	maheshpalv	`end`
89
90			`LE_alu : begin
91	9	maheshpalv	`aluOut = op1<=op2 ? 1'b1 : 1'b0;`
92	6	maheshpalv	`end`
93
94			`LT_alu : begin
95	9	maheshpalv	`aluOut = op1<op2 ? 1'b1 : 1'b0;`
96	6	maheshpalv	`end`
97
98			`ADD_alu : begin
99	9	maheshpalv	`aluOut = addRes[7:0];`
100			`carryOut = addRes[8];`
101	6	maheshpalv	`end`
102
103			`SUB_alu : begin
104	9	maheshpalv	`aluOut = subRes[7:0];`
105			`carryOut = subRes[8];`
106	6	maheshpalv	`end`
107
108			`LD_data : begin
109	9	maheshpalv	`aluOut = op2;`
110	6	maheshpalv	`end`
111
112			`default : begin`
113	9	maheshpalv	`aluOut = 16'b0;`
114	8	maheshpalv	`$write ("\nUnknown operation. \tmodule : ALU");`
115	6	maheshpalv	`end`
116			`endcase`
117
118			`end`
119			`else`
120			`begin`
121
122	9	maheshpalv	`aluOut = aluOut;`
123	6	maheshpalv	`end`
124
125	3	maheshpalv	`end`
126
127			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [alu.v] - Blame information for rev 10