URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [alu.v] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log


 
`include "timescale.v"
`include "defines.v"
 
        module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2,
                                output [7:0] aluOut, output carryOut);
 
 
                wire [8:0] operand1 = {1'b0, op1};
                wire [8:0] operand2 = {1'b0, op2};
 
                wire [8:0] addRes = operand1 + operand2;
                wire [8:0] subRes = operand1 - operand2;
 
                reg [8:0] aluOutput;
                reg carryOutput;
 
                always @ (op1 or op2 or aluOpcode)
                begin
 
 
 
                case (aluOpcode)
 
                `AND_alu        :       begin
                                                aluOutput = op1 & op2;
                                                end
 
                `OR_alu         :       begin
                                                aluOutput = op1 | op2;
                                                end
 
                `XOR_alu        :       begin
                                                aluOutput = op1^op2;
                                                end
 
                `GT_alu         :       begin
                                                aluOutput = op1>op2 ? 1'b1 : 1'b0;
                                                end
 
                `GE_alu         :       begin
                                                aluOutput = op1>=op2 ? 1'b1 : 1'b0;
                                                end
 
                `EQ_alu         :       begin
                                                aluOutput = op1==op2 ? 1'b1 : 1'b0;
                                                end
 
                `LE_alu         :       begin
                                                aluOutput = op1<=op2 ? 1'b1 : 1'b0;
                                                end
 
                `LT_alu         :       begin
                                                aluOutput = op1<op2 ? 1'b1 : 1'b0;
                                                end
 
                `ADD_alu        :       begin
                                                aluOutput = addRes[7:0];
                                                carryOutput = addRes[8];
                                                end
 
                `SUB_alu        :       begin
                                                aluOutput = subRes[7:0];
                                                carryOutput = subRes[8];
                                                end
 
                default         :       begin
                                                aluOutput = 16'b0;
                                                $write ("Unknown operation. \nmodule : ALU");
                                                end
                endcase
 
                end
 
                assign aluOut = aluOutput;
                assign carryOut = carryOutput;
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5			module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2,
6			`output [7:0] aluOut, output carryOut);`
7
8
9			`wire [8:0] operand1 = {1'b0, op1};`
10			`wire [8:0] operand2 = {1'b0, op2};`
11
12			`wire [8:0] addRes = operand1 + operand2;`
13			`wire [8:0] subRes = operand1 - operand2;`
14
15			`reg [8:0] aluOutput;`
16			`reg carryOutput;`
17
18			`always @ (op1 or op2 or aluOpcode)`
19			`begin`
20
21
22
23			`case (aluOpcode)`
24
25			`AND_alu : begin
26			`aluOutput = op1 & op2;`
27			`end`
28
29			`OR_alu : begin
30			`aluOutput = op1 \| op2;`
31			`end`
32
33			`XOR_alu : begin
34			`aluOutput = op1^op2;`
35			`end`
36
37			`GT_alu : begin
38			`aluOutput = op1>op2 ? 1'b1 : 1'b0;`
39			`end`
40
41			`GE_alu : begin
42			`aluOutput = op1>=op2 ? 1'b1 : 1'b0;`
43			`end`
44
45			`EQ_alu : begin
46			`aluOutput = op1==op2 ? 1'b1 : 1'b0;`
47			`end`
48
49			`LE_alu : begin
50			`aluOutput = op1<=op2 ? 1'b1 : 1'b0;`
51			`end`
52
53			`LT_alu : begin
54			`aluOutput = op1<op2 ? 1'b1 : 1'b0;`
55			`end`
56
57			`ADD_alu : begin
58			`aluOutput = addRes[7:0];`
59			`carryOutput = addRes[8];`
60			`end`
61
62			`SUB_alu : begin
63			`aluOutput = subRes[7:0];`
64			`carryOutput = subRes[8];`
65			`end`
66
67			`default : begin`
68			`aluOutput = 16'b0;`
69			`$write ("Unknown operation. \nmodule : ALU");`
70			`end`
71			`endcase`
72
73			`end`
74
75			`assign aluOut = aluOutput;`
76			`assign carryOut = carryOutput;`
77
78			`endmodule`

Browse

Tools

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [alu.v] - Blame information for rev 3