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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [alu.v] - Blame information for rev 7

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`include "timescale.v"
`include "defines.v"
 
        module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn,
                                output [7:0] aluOut, output carryOut);
 
 
                wire [8:0] operand1 = {1'b0, op1};
                wire [8:0] operand2 = {1'b0, op2};
 
                wire [8:0] addRes = operand1 + operand2;
                wire [8:0] subRes = operand1 - operand2;
 
                reg [8:0] aluOutput;
                reg carryOutput;
 
                always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)
                begin
 
 
                if (aluEn)
                begin
 
                                case (aluOpcode)
 
                                `AND_alu        :       begin
                                                                aluOutput = op1 & op2;
                                                                end
 
                                `OR_alu         :       begin
                                                                aluOutput = op1 | op2;
                                                                end
 
                                `XOR_alu        :       begin
                                                                aluOutput = op1^op2;
                                                                end
 
                                `GT_alu         :       begin
                                                                aluOutput = op1>op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `GE_alu         :       begin
                                                                aluOutput = op1>=op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `EQ_alu         :       begin
                                                                aluOutput = op1==op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `LE_alu         :       begin
                                                                aluOutput = op1<=op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `LT_alu         :       begin
                                                                aluOutput = op1<op2 ? 1'b1 : 1'b0;
                                                                end
 
                                `ADD_alu        :       begin
                                                                aluOutput = addRes[7:0];
                                                                carryOutput = addRes[8];
                                                                end
 
                                `SUB_alu        :       begin
                                                                aluOutput = subRes[7:0];
                                                                carryOutput = subRes[8];
                                                                end
 
                                `LD_data        :       begin
                                                                aluOutput = op1;
                                                                end
 
                                default         :       begin
                                                                aluOutput = 16'b0;
                                                                $write ("Unknown operation. \nmodule : ALU");
                                                                end
                                endcase
 
                        end
                        else
                        begin
 
                                aluOutput = aluOutput;
                        end
 
                end
 
                assign aluOut = aluOutput;
                assign carryOut = carryOutput;
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5	6	maheshpalv	module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn,
6	3	maheshpalv	`output [7:0] aluOut, output carryOut);`
7
8
9			`wire [8:0] operand1 = {1'b0, op1};`
10			`wire [8:0] operand2 = {1'b0, op2};`
11
12			`wire [8:0] addRes = operand1 + operand2;`
13			`wire [8:0] subRes = operand1 - operand2;`
14
15			`reg [8:0] aluOutput;`
16			`reg carryOutput;`
17
18	7	maheshpalv	`always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)`
19	3	maheshpalv	`begin`
20
21
22	6	maheshpalv	`if (aluEn)`
23			`begin`
24
25			`case (aluOpcode)`
26
27			`AND_alu : begin
28			`aluOutput = op1 & op2;`
29			`end`
30
31			`OR_alu : begin
32			`aluOutput = op1 \| op2;`
33			`end`
34
35			`XOR_alu : begin
36			`aluOutput = op1^op2;`
37			`end`
38
39			`GT_alu : begin
40			`aluOutput = op1>op2 ? 1'b1 : 1'b0;`
41			`end`
42
43			`GE_alu : begin
44			`aluOutput = op1>=op2 ? 1'b1 : 1'b0;`
45			`end`
46
47			`EQ_alu : begin
48			`aluOutput = op1==op2 ? 1'b1 : 1'b0;`
49			`end`
50
51			`LE_alu : begin
52			`aluOutput = op1<=op2 ? 1'b1 : 1'b0;`
53			`end`
54
55			`LT_alu : begin
56			`aluOutput = op1<op2 ? 1'b1 : 1'b0;`
57			`end`
58
59			`ADD_alu : begin
60			`aluOutput = addRes[7:0];`
61			`carryOutput = addRes[8];`
62			`end`
63
64			`SUB_alu : begin
65			`aluOutput = subRes[7:0];`
66			`carryOutput = subRes[8];`
67			`end`
68
69			`LD_data : begin
70			`aluOutput = op1;`
71			`end`
72
73			`default : begin`
74			`aluOutput = 16'b0;`
75			`$write ("Unknown operation. \nmodule : ALU");`
76			`end`
77			`endcase`
78
79			`end`
80			`else`
81			`begin`
82
83			`aluOutput = aluOutput;`
84			`end`
85
86	3	maheshpalv	`end`
87
88			`assign aluOut = aluOutput;`
89			`assign carryOut = carryOutput;`
90
91			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [alu.v] - Blame information for rev 7