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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [bitNegator.v] - Blame information for rev 8

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`include "timescale.v"
`include "defines.v"
 
module bitNegator (bitIn, bitN, bitOut);
 
        input bitIn, bitN;
        output bitOut;
 
        reg bitOut;
 
 
        always @ (bitIn or bitN)
        begin
 
                if (bitN)
                begin
                        bitOut = ~ bitIn;
                end
                else
                begin
                        bitOut = bitIn;
                end
 
        end
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5			`module bitNegator (bitIn, bitN, bitOut);`
6
7			`input bitIn, bitN;`
8			`output bitOut;`
9
10			`reg bitOut;`
11
12
13			`always @ (bitIn or bitN)`
14			`begin`
15
16			`if (bitN)`
17			`begin`
18			`bitOut = ~ bitIn;`
19			`end`
20			`else`
21			`begin`
22			`bitOut = bitIn;`
23			`end`
24
25			`end`
26
27			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [bitNegator.v] - Blame information for rev 8