URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [byteNegator.v] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log


 
`include "timescale.v"
`include "defines.v"
 
module byteNegator (byteIn, byteN, byteOut);
 
        input [7:0]      byteIn;
        input byteN;
 
        output [7:0] byteOut;
 
        reg [7:0] byteOut;
 
 
        always @ (byteIn or byteN)
        begin
 
                if (byteN)
                begin
                        byteOut = ~ byteIn;
                end
                else
                begin
                        byteOut = byteIn;
                end
 
        end
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5			`module byteNegator (byteIn, byteN, byteOut);`
6
7			`input [7:0] byteIn;`
8			`input byteN;`
9
10			`output [7:0] byteOut;`
11
12			`reg [7:0] byteOut;`
13
14
15			`always @ (byteIn or byteN)`
16			`begin`
17
18			`if (byteN)`
19			`begin`
20			`byteOut = ~ byteIn;`
21			`end`
22			`else`
23			`begin`
24			`byteOut = byteIn;`
25			`end`
26
27			`end`
28
29			`endmodule`

Browse

Tools

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [byteNegator.v] - Blame information for rev 3