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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
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////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
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////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
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////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
 
module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
                                                        branch,
                                                        accMuxSel, accEn, op2MuxSel, aluEn, aluOpcode,
                                                        bitRamEn, bitRamRw, byteRamEn, byteRamRw,
                                                        inputRead, outputRw
 
                                                        `ifdef timerAndCounter_peripheral
                                                                , entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn
                                                        `endif
 
                                                        `ifdef UART_peripheral
                                                                , uartRead, uartWrite
                                                        `endif
 
                                                        `ifdef SPI_peripheral
                                                                , sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift
                                                        `endif
 
                                                        );
 
 
        input clk, reset;
        input [`instOpCodeLen-1:0] instOpCode;
        input acc0;
        input [1:0] iomemCode;
 
        output branch;
        output [`accMuxSelLen-1:0]       accMuxSel;
        output accEn;
        output [`op2MuxSelLen-1:0]       op2MuxSel;
        output aluEn;
        output [`aluOpcodeLen-1:0] aluOpcode;
        output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
        output inputRead, outputRw;
 
        `ifdef timerAndCounter_peripheral
        output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
        `endif
 
        `ifdef UART_peripheral
        output uartRead, uartWrite;
        `endif
 
        `ifdef SPI_peripheral
        output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
        `endif
 
        reg branch;
        reg [`accMuxSelLen-1:0]  accMuxSel;
        reg accEn;
        reg [`op2MuxSelLen-1:0]  op2MuxSel;
        reg aluEn;
        reg [`aluOpcodeLen-1:0] aluOpcode;
        reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
        reg inputRead, outputRw;
 
        `ifdef timerAndCounter_peripheral
        reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
        `endif
 
        `ifdef UART_peripheral
        reg uartRead, uartWrite;
        `endif
 
        `ifdef SPI_peripheral
        reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
        `endif
 
        reg [`cuStateLen-1:0] state;
 
        // control unit FSM states:
 
        parameter       s               = `cuStateLen'b0;
        parameter       sTc     = `cuStateLen'b1;
        parameter       sBr     = `cuStateLen'b10;
        parameter       sLd     = `cuStateLen'b11;
        parameter       sSt     = `cuStateLen'b100;
        parameter       sUart   = `cuStateLen'b101;
        parameter       sSpi    = `cuStateLen'b110;
        parameter       sAlu    = `cuStateLen'b111;
 
 
 
 
        always @ (negedge clk)
        begin
 
 
                if (reset)
                begin
                        state = s;
 
                        branch = 0;      accMuxSel = 0;   accEn = 0;       op2MuxSel = 0;   aluEn = 0; aluOpcode = 0; bitRamEn = 0;
                        bitRamRw = 1;   byteRamEn = 0;   byteRamRw = 1;  inputRead = 0;   outputRw = 1;
 
                        `ifdef timeAndCounter_peripheral
                                entypeEn = 0;    tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                        `endif
 
                        `ifdef UART_peripheral
                                uartRead = 0;    uartWrite = 0;
                        `endif
 
                        `ifdef SPI_peripheral
                                sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                        `endif
                end
 
                else
                begin
 
                        // execution unit control signals
 
                        case (state)
 
                        s               :               begin
 
 
                                case (instOpCode)
 
                                `END                    :       begin
 
                                                state = sBr;
 
                                                branch = 1;                     // branch to some address . . .
                                                accMuxSel = 0;
                                                accEn = 0;
                                                op2MuxSel = 0;
                                                aluEn = 0;
                                                aluOpcode = 0;
                                                bitRamEn = 0;
                                                bitRamRw = 1;
                                                byteRamEn = 0;
                                                byteRamRw = 1;
                                                inputRead = 0;
                                                outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0;
                                                        spiBufShift = 0;
                                                `endif
 
                                end     // end case END
 
 
 
                                `JMP                    :       begin
 
                                                state = sBr;
 
                                                if (acc0)
                                                        branch = 1;                     // branch to some address . . .
                                                else
                                                        branch = 0;
                                                accMuxSel = 0;
                                                accEn = 0;
                                                op2MuxSel = 0;
                                                aluEn = 0;
                                                aluOpcode = 0;
                                                bitRamEn = 0;
                                                bitRamRw = 1;
                                                byteRamEn = 0;
                                                byteRamRw = 1;
                                                inputRead = 0;
                                                outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end     // end case JMP
 
 
 
                                `Ld                     :       begin
                                // load thr. op2 MUX and alu.... enable acc in next cycle
                                                state = sAlu;
 
                                                branch = 0;
//                                              accMuxSel = `accMuxSelAluOut;
                                                accMuxSel = 0;
                                                accEn = 0;
 
                                                        case (iomemCode)
                                                        2'b00   :       op2MuxSel = `op2MuxSelInput;
                                                        2'b01   :       op2MuxSel = `op2MuxSelOutput;
                                                        2'b10   :       op2MuxSel = `op2MuxSelBitRam;
                                                        2'b11   :       op2MuxSel = `op2MuxSelByteRam;
                                                        default:        op2MuxSel = `op2MuxSelInput;
                                                        endcase
                                                        aluEn = 1'b1;
                                                        aluOpcode = `LD_data;
 
                                                bitRamEn = 1'b1;
                                                bitRamRw = 1'b1;
                                                byteRamEn = 1'b1;
                                                byteRamRw = 1'b1;
                                                inputRead = 1'b1;
                                                outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end     // end case Ld
 
 
 
 
                                `Ldi                    :       begin
                                                state = sLd;
 
                                                branch = 1'b0;
                                                        accMuxSel = `accMuxSelImmData;  // select imm data thr mux
                                                        accEn = 1'b1;           // acc enabled
                                                op2MuxSel = 1'b0;
                                                aluOpcode = 1'b0;
                                                aluEn = 1'b0;
                                                bitRamEn = 1'b0;
                                                bitRamRw = 1'b1;
                                                byteRamEn = 1'b0;
                                                byteRamRw = 1'b1;
                                                inputRead = 1'b0;
                                                outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end             // end case Ldi
 
 
 
                                `ST                     :       begin
                                                state = sSt;
 
                                                branch = 1'b0;
                                                accMuxSel = 1'b0;
                                                accEn = 1'b0;
                                                op2MuxSel = 1'b0;
                                                aluEn = 1'b0;
                                                aluOpcode = 1'b0;
                                                inputRead = 1'b0;
 
                                                        case (iomemCode)
                                                        2'b10   :       begin   bitRamRw = 1'b0;        byteRamRw = 1'b1;       outputRw = 1'b1; bitRamEn = 1'b1;       byteRamEn = 1'b1;       end
                                                        2'b11   :       begin   bitRamRw = 1'b1;        byteRamRw = 1'b0;       outputRw = 1'b1; bitRamEn = 1'b1;       byteRamEn = 1'b1;       end
                                                        2'b01   :       begin   bitRamRw = 1'b1;        byteRamRw = 1'b1;       outputRw = 1'b0; end
                                                        default:        begin   bitRamRw = 1'b1;        byteRamRw = 1'b1;       outputRw = 1'b1;        end
                                                        endcase
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
                                `ADD                    :       begin
                                                state = sAlu;
                                                aluOpcode = `ADD_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
                                `SUB                    :       begin
                                                state = sAlu;
                                                aluOpcode = `SUB_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
                                // MUL & DIV are not implemented
 
 
 
                                `AND                    :       begin
                                                state = sAlu;
                                                aluOpcode = `AND_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
                                `OR                     :       begin
                                                state = sAlu;
                                                aluOpcode = `OR_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
                                `XOR                    :       begin
                                                state = sAlu;
                                                aluOpcode = `XOR_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
                                `GrT                    :       begin
                                                state = sAlu;
                                                aluOpcode = `GT_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
 
 
                                `GE                     :       begin
                                                state = sAlu;
                                                aluOpcode = `GE_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
 
 
                                `EQ                     :       begin
                                                state = sAlu;
                                                aluOpcode = `EQ_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
 
 
                                `LE                     :       begin
                                                state = sAlu;
                                                aluOpcode = `LE_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
 
 
                                `LT                     :       begin
                                                state = sAlu;
                                                aluOpcode = `LT_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
                                `ifdef timeAndCounter_peripheral
                                `PRE                    :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b1;      tcLoadEn = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
                                `ifdef timeAndCounter_peripheral
                                `ETY                    :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b1;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `RST                    :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b1;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `LdTC                   :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b1;
 
                                                accMuxSel = `accMuxSelTcLoad;           accEn = 1'b1;   // loading TC status data
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;                  op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `LdACC                  :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b0;                tcAccRead = 1'b1;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
 
                                                accMuxSel = `accMuxSelTcAcc;            accEn = 1'b1;   // loading TC ACC data
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef UART_peripheral
                                `UARTrd                 :       begin
                                                state = sUart;
 
                                                uartRead = 1'b1;                uartWrite = 1'b0;
 
                                                accMuxSel = `accMuxSelUartData;         accEn = 1'b1;   // loading UART data
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef UART_peripheral
                                `UARTstat                       :       begin
                                                state = sUart;
 
                                                uartRead = 1'b0;                uartWrite = 1'b0;
 
                                                accMuxSel = `accMuxSelUartStat;         accEn = 1'b1;   // loading UART status
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef UART_peripheral
                                `UARTwr                 :       begin
                                                state = sUart;
 
                                                uartRead = 1'b0;                uartWrite = 1'b1;
 
                                                aluEn = 1'b0;   aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef SPI_peripheral
                                `SPIxFER                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1'b1;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIstat                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1'b0;          spiStatRead = 1'b1;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIwBUF                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b1;     spiBufShift = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIrBUF                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b1;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                end
                                `endif
 
                                default         :       begin
 
                                $write ("\n", $time, "ns unknown/unused instruction op-code encountered by control unit");
//                              $stop;
                                end
                                endcase // end  case (instOpCode)
 
 
 
                        end     // end case (s)
 
 
                        sBr             :       begin
                                                        branch = 1'b0;
                                                        state = s;
                                                        end             // end case sBr
 
 
                        sLd             :       begin
                                                        accEn = 1'b0;
                                                        state = s;
                                                        end             // end case sLd
 
                        sSt             :       begin
                                                        bitRamRw = 1'b1;        byteRamRw = 1'b1; outputRw = 1'b1;
                                                        state = s;
                                                        end
 
                        sAlu            :       begin
                                                        aluEn = 1'b0;
                                                        accEn = 1'b1;
                                                        accMuxSel = `accMuxSelAluOut;
                                                        state = s;
                                                        end
 
                        `ifdef timerAndCounter_peripheral
                        sTc             :       begin
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                        state = s;
                                                        end
                        `endif
 
                        `ifdef UART_peripheral
                        sUart           :       begin
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                        state = s;
                                                        end
                        `endif
 
                        `ifdef SPI_peripheral
                        sSpi            :       begin
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                        state = s;
                                                        end
                        `endif
 
                        default         :       begin
                        $write ("       control unit FSM in unknown state.      ");
                        end
                        endcase // end  case (state)
                end     // end else part (outermost)
 
 
 
        end     // end always
 
 
endmodule

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40	3	maheshpalv
41			`include "timescale.v"
42			`include "defines.v"
43
44
45	5	maheshpalv	`module controlUnit (clk, reset, instOpCode, acc0, iomemCode,`
46	3	maheshpalv	`branch,`
47	6	maheshpalv	`accMuxSel, accEn, op2MuxSel, aluEn, aluOpcode,`
48	3	maheshpalv	`bitRamEn, bitRamRw, byteRamEn, byteRamRw,`
49			`inputRead, outputRw`
50
51			`ifdef timerAndCounter_peripheral
52			`, entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn`
53			`endif
54
55			`ifdef UART_peripheral
56			`, uartRead, uartWrite`
57			`endif
58
59			`ifdef SPI_peripheral
60			`, sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift`
61			`endif
62
63			`);`
64
65
66			`input clk, reset;`
67			input [`instOpCodeLen-1:0] instOpCode;
68			`input acc0;`
69			`input [1:0] iomemCode;`
70
71			`output branch;`
72			output [`accMuxSelLen-1:0] accMuxSel;
73			`output accEn;`
74			output [`op2MuxSelLen-1:0] op2MuxSel;
75	6	maheshpalv	`output aluEn;`
76	3	maheshpalv	output [`aluOpcodeLen-1:0] aluOpcode;
77			`output bitRamEn, bitRamRw, byteRamEn, byteRamRw;`
78			`output inputRead, outputRw;`
79
80			`ifdef timerAndCounter_peripheral
81			`output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;`
82	5	maheshpalv	`endif
83	3	maheshpalv
84			`ifdef UART_peripheral
85			`output uartRead, uartWrite;`
86			`endif
87
88			`ifdef SPI_peripheral
89			`output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;`
90			`endif
91	5	maheshpalv
92			`reg branch;`
93			reg [`accMuxSelLen-1:0] accMuxSel;
94			`reg accEn;`
95			reg [`op2MuxSelLen-1:0] op2MuxSel;
96	6	maheshpalv	`reg aluEn;`
97	5	maheshpalv	reg [`aluOpcodeLen-1:0] aluOpcode;
98			`reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;`
99			`reg inputRead, outputRw;`
100
101			`ifdef timerAndCounter_peripheral
102			`reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;`
103			`endif
104
105			`ifdef UART_peripheral
106			`reg uartRead, uartWrite;`
107			`endif
108	3	maheshpalv
109	5	maheshpalv	`ifdef SPI_peripheral
110			`reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;`
111			`endif
112
113			reg [`cuStateLen-1:0] state;
114
115			`// control unit FSM states:`
116
117			parameter s = `cuStateLen'b0;
118			parameter sTc = `cuStateLen'b1;
119			parameter sBr = `cuStateLen'b10;
120			parameter sLd = `cuStateLen'b11;
121			parameter sSt = `cuStateLen'b100;
122			parameter sUart = `cuStateLen'b101;
123			parameter sSpi = `cuStateLen'b110;
124			parameter sAlu = `cuStateLen'b111;
125
126
127
128
129			`always @ (negedge clk)`
130			`begin`
131
132
133			`if (reset)`
134			`begin`
135			`state = s;`
136
137	6	maheshpalv	`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluEn = 0; aluOpcode = 0; bitRamEn = 0;`
138	5	maheshpalv	`bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
139
140			`ifdef timeAndCounter_peripheral
141			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
142			`endif
143
144			`ifdef UART_peripheral
145			`uartRead = 0; uartWrite = 0;`
146			`endif
147
148			`ifdef SPI_peripheral
149			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
150			`endif
151			`end`
152
153			`else`
154			`begin`
155
156			`// execution unit control signals`
157
158			`case (state)`
159
160			`s : begin`
161
162	3	maheshpalv
163	5	maheshpalv	`case (instOpCode)`
164
165			`END : begin
166
167			`state = sBr;`
168
169			`branch = 1; // branch to some address . . .`
170			`accMuxSel = 0;`
171			`accEn = 0;`
172			`op2MuxSel = 0;`
173	6	maheshpalv	`aluEn = 0;`
174	5	maheshpalv	`aluOpcode = 0;`
175			`bitRamEn = 0;`
176			`bitRamRw = 1;`
177			`byteRamEn = 0;`
178			`byteRamRw = 1;`
179			`inputRead = 0;`
180			`outputRw = 1;`
181
182			`ifdef timeAndCounter_peripheral
183			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
184			`endif
185
186			`ifdef UART_peripheral
187			`uartRead = 0; uartWrite = 0;`
188			`endif
189
190			`ifdef SPI_peripheral
191			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0;`
192			`spiBufShift = 0;`
193			`endif
194
195			`end // end case END`
196	3	maheshpalv
197
198	5	maheshpalv
199			`JMP : begin
200
201			`state = sBr;`
202
203	6	maheshpalv	`if (acc0)`
204			`branch = 1; // branch to some address . . .`
205			`else`
206			`branch = 0;`
207	5	maheshpalv	`accMuxSel = 0;`
208			`accEn = 0;`
209			`op2MuxSel = 0;`
210	6	maheshpalv	`aluEn = 0;`
211	5	maheshpalv	`aluOpcode = 0;`
212			`bitRamEn = 0;`
213			`bitRamRw = 1;`
214			`byteRamEn = 0;`
215			`byteRamRw = 1;`
216			`inputRead = 0;`
217			`outputRw = 1;`
218
219			`ifdef timeAndCounter_peripheral
220			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
221			`endif
222
223			`ifdef UART_peripheral
224			`uartRead = 0; uartWrite = 0;`
225			`endif
226
227			`ifdef SPI_peripheral
228			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
229			`endif
230
231			`end // end case JMP`
232
233
234
235			`Ld : begin
236			`// load thr. op2 MUX and alu.... enable acc in next cycle`
237	9	maheshpalv	`state = sAlu;`
238	5	maheshpalv
239			`branch = 0;`
240	9	maheshpalv	// accMuxSel = `accMuxSelAluOut;
241	5	maheshpalv	`accMuxSel = 0;`
242			`accEn = 0;`
243
244			`case (iomemCode)`
245			2'b00 : op2MuxSel = `op2MuxSelInput;
246			2'b01 : op2MuxSel = `op2MuxSelOutput;
247			2'b10 : op2MuxSel = `op2MuxSelBitRam;
248			2'b11 : op2MuxSel = `op2MuxSelByteRam;
249			default: op2MuxSel = `op2MuxSelInput;
250			`endcase`
251	7	maheshpalv	`aluEn = 1'b1;`
252	5	maheshpalv	aluOpcode = `LD_data;
253
254	7	maheshpalv	`bitRamEn = 1'b1;`
255			`bitRamRw = 1'b1;`
256			`byteRamEn = 1'b1;`
257			`byteRamRw = 1'b1;`
258			`inputRead = 1'b1;`
259			`outputRw = 1'b1;`
260	5	maheshpalv
261			`ifdef timeAndCounter_peripheral
262	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
263	5	maheshpalv	`endif
264
265			`ifdef UART_peripheral
266	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
267	5	maheshpalv	`endif
268
269			`ifdef SPI_peripheral
270	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
271	5	maheshpalv	`endif
272
273			`end // end case Ld`
274
275
276
277
278			`Ldi : begin
279	9	maheshpalv	`state = sLd;`
280	5	maheshpalv
281	7	maheshpalv	`branch = 1'b0;`
282	5	maheshpalv	accMuxSel = `accMuxSelImmData; // select imm data thr mux
283	7	maheshpalv	`accEn = 1'b1; // acc enabled`
284			`op2MuxSel = 1'b0;`
285			`aluOpcode = 1'b0;`
286			`aluEn = 1'b0;`
287			`bitRamEn = 1'b0;`
288			`bitRamRw = 1'b1;`
289			`byteRamEn = 1'b0;`
290			`byteRamRw = 1'b1;`
291			`inputRead = 1'b0;`
292			`outputRw = 1'b1;`
293	5	maheshpalv
294			`ifdef timeAndCounter_peripheral
295	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
296	5	maheshpalv	`endif
297
298			`ifdef UART_peripheral
299	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
300	5	maheshpalv	`endif
301
302			`ifdef SPI_peripheral
303	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
304	5	maheshpalv	`endif
305
306			`end // end case Ldi`
307
308
309
310			`ST : begin
311			`state = sSt;`
312
313	7	maheshpalv	`branch = 1'b0;`
314			`accMuxSel = 1'b0;`
315			`accEn = 1'b0;`
316			`op2MuxSel = 1'b0;`
317			`aluEn = 1'b0;`
318			`aluOpcode = 1'b0;`
319			`inputRead = 1'b0;`
320	5	maheshpalv
321			`case (iomemCode)`
322	9	maheshpalv	`2'b10 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end`
323			`2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end`
324			`2'b01 : begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b0; end`
325	7	maheshpalv	`default: begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1; end`
326	5	maheshpalv	`endcase`
327
328			`ifdef timeAndCounter_peripheral
329	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
330	5	maheshpalv	`endif
331
332			`ifdef UART_peripheral
333	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
334	5	maheshpalv	`endif
335
336			`ifdef SPI_peripheral
337	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
338	5	maheshpalv	`endif
339
340			`end`
341
342
343
344			`ADD : begin
345			`state = sAlu;`
346			aluOpcode = `ADD_alu;
347	7	maheshpalv	`aluEn = 1'b1;`
348			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
349			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
350	5	maheshpalv
351			`ifdef timeAndCounter_peripheral
352	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
353	5	maheshpalv	`endif
354
355			`ifdef UART_peripheral
356	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
357	5	maheshpalv	`endif
358
359			`ifdef SPI_peripheral
360	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
361	5	maheshpalv	`endif
362
363			`end`
364
365
366			`SUB : begin
367			`state = sAlu;`
368			aluOpcode = `SUB_alu;
369	7	maheshpalv	`aluEn = 1'b1;`
370			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
371			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
372	5	maheshpalv
373			`ifdef timeAndCounter_peripheral
374	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
375	5	maheshpalv	`endif
376
377			`ifdef UART_peripheral
378	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
379	5	maheshpalv	`endif
380
381			`ifdef SPI_peripheral
382	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
383	5	maheshpalv	`endif
384
385			`end`
386
387			`// MUL & DIV are not implemented`
388
389
390
391			`AND : begin
392			`state = sAlu;`
393			aluOpcode = `AND_alu;
394	7	maheshpalv	`aluEn = 1'b1;`
395			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
396			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
397	5	maheshpalv
398			`ifdef timeAndCounter_peripheral
399	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
400	5	maheshpalv	`endif
401
402			`ifdef UART_peripheral
403	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
404	5	maheshpalv	`endif
405
406			`ifdef SPI_peripheral
407	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
408	5	maheshpalv	`endif
409
410			`end`
411
412
413
414			`OR : begin
415			`state = sAlu;`
416			aluOpcode = `OR_alu;
417	7	maheshpalv	`aluEn = 1'b1;`
418			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
419			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
420	5	maheshpalv
421			`ifdef timeAndCounter_peripheral
422	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
423	5	maheshpalv	`endif
424
425			`ifdef UART_peripheral
426	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
427	5	maheshpalv	`endif
428
429			`ifdef SPI_peripheral
430	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
431	5	maheshpalv	`endif
432
433			`end`
434
435
436
437			`XOR : begin
438			`state = sAlu;`
439			aluOpcode = `XOR_alu;
440	7	maheshpalv	`aluEn = 1'b1;`
441			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
442			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
443	5	maheshpalv
444			`ifdef timeAndCounter_peripheral
445	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
446	5	maheshpalv	`endif
447
448			`ifdef UART_peripheral
449	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
450	5	maheshpalv	`endif
451
452			`ifdef SPI_peripheral
453	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
454	5	maheshpalv	`endif
455
456			`end`
457
458
459
460			`GrT : begin
461			`state = sAlu;`
462			aluOpcode = `GT_alu;
463	7	maheshpalv	`aluEn = 1'b1;`
464			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
465			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
466	5	maheshpalv
467			`ifdef timeAndCounter_peripheral
468	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
469	5	maheshpalv	`endif
470
471			`ifdef UART_peripheral
472	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
473	5	maheshpalv	`endif
474
475			`ifdef SPI_peripheral
476	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
477	5	maheshpalv	`endif
478
479			`end`
480
481
482
483
484
485			`GE : begin
486			`state = sAlu;`
487			aluOpcode = `GE_alu;
488	7	maheshpalv	`aluEn = 1'b1;`
489			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
490			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
491	5	maheshpalv
492			`ifdef timeAndCounter_peripheral
493	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
494	5	maheshpalv	`endif
495
496			`ifdef UART_peripheral
497	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
498	5	maheshpalv	`endif
499
500			`ifdef SPI_peripheral

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