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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [controlUnit.v] - Blame information for rev 5

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`include "timescale.v"
`include "defines.v"
 
 
module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
                                                        branch,
                                                        accMuxSel, accEn, op2MuxSel, aluOpcode,
                                                        bitRamEn, bitRamRw, byteRamEn, byteRamRw,
                                                        inputRead, outputRw
 
                                                        `ifdef timerAndCounter_peripheral
                                                                , entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn
                                                        `endif
 
                                                        `ifdef UART_peripheral
                                                                , uartRead, uartWrite
                                                        `endif
 
                                                        `ifdef SPI_peripheral
                                                                , sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift
                                                        `endif
 
                                                        );
 
 
        input clk, reset;
        input [`instOpCodeLen-1:0] instOpCode;
        input acc0;
        input [1:0] iomemCode;
 
        output branch;
        output [`accMuxSelLen-1:0]       accMuxSel;
        output accEn;
        output [`op2MuxSelLen-1:0]       op2MuxSel;
        output [`aluOpcodeLen-1:0] aluOpcode;
        output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
        output inputRead, outputRw;
 
        `ifdef timerAndCounter_peripheral
        output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
        `endif
 
        `ifdef UART_peripheral
        output uartRead, uartWrite;
        `endif
 
        `ifdef SPI_peripheral
        output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
        `endif
 
        reg branch;
        reg [`accMuxSelLen-1:0]  accMuxSel;
        reg accEn;
        reg [`op2MuxSelLen-1:0]  op2MuxSel;
        reg [`aluOpcodeLen-1:0] aluOpcode;
        reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
        reg inputRead, outputRw;
 
        `ifdef timerAndCounter_peripheral
        reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
        `endif
 
        `ifdef UART_peripheral
        reg uartRead, uartWrite;
        `endif
 
        `ifdef SPI_peripheral
        reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
        `endif
 
        reg [`cuStateLen-1:0] state;
 
        // control unit FSM states:
 
        parameter       s               = `cuStateLen'b0;
        parameter       sTc     = `cuStateLen'b1;
        parameter       sBr     = `cuStateLen'b10;
        parameter       sLd     = `cuStateLen'b11;
        parameter       sSt     = `cuStateLen'b100;
        parameter       sUart   = `cuStateLen'b101;
        parameter       sSpi    = `cuStateLen'b110;
        parameter       sAlu    = `cuStateLen'b111;
 
 
 
 
        always @ (negedge clk)
        begin
 
 
                if (reset)
                begin
                        state = s;
 
                        branch = 0;      accMuxSel = 0;   accEn = 0;       op2MuxSel = 0;   aluOpcode = 0;   bitRamEn = 0;
                        bitRamRw = 1;   byteRamEn = 0;   byteRamRw = 1;  inputRead = 0;   outputRw = 1;
 
                        `ifdef timeAndCounter_peripheral
                                entypeEn = 0;    tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                        `endif
 
                        `ifdef UART_peripheral
                                uartRead = 0;    uartWrite = 0;
                        `endif
 
                        `ifdef SPI_peripheral
                                sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                        `endif
                end
 
                else
                begin
 
                        // execution unit control signals
 
                        case (state)
 
                        s               :               begin
 
 
                                case (instOpCode)
 
                                `END                    :       begin
 
                                                state = sBr;
 
                                                branch = 1;                     // branch to some address . . .
                                                accMuxSel = 0;
                                                accEn = 0;
                                                op2MuxSel = 0;
                                                aluOpcode = 0;
                                                bitRamEn = 0;
                                                bitRamRw = 1;
                                                byteRamEn = 0;
                                                byteRamRw = 1;
                                                inputRead = 0;
                                                outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0;
                                                        spiBufShift = 0;
                                                `endif
 
                                end     // end case END
 
 
 
                                `JMP                    :       begin
 
                                                state = sBr;
 
                                                branch = 1;                     // branch to some address . . .
                                                accMuxSel = 0;
                                                accEn = 0;
                                                op2MuxSel = 0;
                                                aluOpcode = 0;
                                                bitRamEn = 0;
                                                bitRamRw = 1;
                                                byteRamEn = 0;
                                                byteRamRw = 1;
                                                inputRead = 0;
                                                outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end     // end case JMP
 
 
 
                                `Ld                     :       begin
                                // load thr. op2 MUX and alu.... enable acc in next cycle
                                                state = sLd;
 
                                                branch = 0;
                                                accMuxSel = 0;
                                                accEn = 0;
 
                                                        case (iomemCode)
                                                        2'b00   :       op2MuxSel = `op2MuxSelInput;
                                                        2'b01   :       op2MuxSel = `op2MuxSelOutput;
                                                        2'b10   :       op2MuxSel = `op2MuxSelBitRam;
                                                        2'b11   :       op2MuxSel = `op2MuxSelByteRam;
                                                        default:        op2MuxSel = `op2MuxSelInput;
                                                        endcase
 
                                                        aluOpcode = `LD_data;
 
                                                bitRamEn = 0;
                                                bitRamRw = 1;
                                                byteRamEn = 0;
                                                byteRamRw = 1;
                                                inputRead = 0;
                                                outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end     // end case Ld
 
 
 
 
                                `Ldi                    :       begin
                                                state = sAlu;
 
                                                branch = 0;
                                                        accMuxSel = `accMuxSelImmData;  // select imm data thr mux
                                                        accEn = 1;              // acc enabled
                                                op2MuxSel = 0;
                                                aluOpcode = 0;
                                                bitRamEn = 0;
                                                bitRamRw = 1;
                                                byteRamEn = 0;
                                                byteRamRw = 1;
                                                inputRead = 0;
                                                outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end             // end case Ldi
 
 
 
                                `ST                     :       begin
                                                state = sSt;
 
                                                branch = 0;
                                                accMuxSel = 0;
                                                accEn = 0;
                                                op2MuxSel = 0;
                                                aluOpcode = 0;
                                                bitRamRw = 0;
                                                byteRamRw = 0;
                                                inputRead = 0;
 
                                                        case (iomemCode)
                                                        2'b01   :       begin   bitRamRw = 0;    byteRamRw = 1;  outputRw = 1; end
                                                        2'b10   :       begin   bitRamRw = 1;   byteRamRw = 0;   outputRw = 1; end
                                                        2'b11   :       begin   bitRamRw = 1;   byteRamRw = 1;  outputRw = 0; end
                                                        default:        begin   bitRamRw = 1;   byteRamRw = 1;  outputRw = 1;   end
                                                        endcase
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
 
                                `ADD                    :       begin
                                                state = sAlu;
                                                aluOpcode = `ADD_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
                                `SUB                    :       begin
                                                state = sAlu;
                                                aluOpcode = `SUB_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
                                // MUL & DIV are not implemented
 
 
 
                                `AND                    :       begin
                                                state = sAlu;
                                                aluOpcode = `AND_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
 
                                `OR                     :       begin
                                                state = sAlu;
                                                aluOpcode = `OR_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
 
                                `XOR                    :       begin
                                                state = sAlu;
                                                aluOpcode = `XOR_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
 
                                `GrT                    :       begin
                                                state = sAlu;
                                                aluOpcode = `GT_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
 
 
 
                                `GE                     :       begin
                                                state = sAlu;
                                                aluOpcode = `GE_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
 
 
 
                                `EQ                     :       begin
                                                state = sAlu;
                                                aluOpcode = `EQ_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
 
 
 
                                `LE                     :       begin
                                                state = sAlu;
                                                aluOpcode = `LE_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
 
 
 
                                `LT                     :       begin
                                                state = sAlu;
                                                aluOpcode = `LT_alu;
 
                                                branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end
 
 
                                `ifdef timeAndCounter_peripheral
                                `PRE                    :       begin
                                                state = sTc;
 
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 1; tcLoadEn = 0;
 
 
                                                aluOpcode = 0;           branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
                                end
                                `endif
 
 
                                `ifdef timeAndCounter_peripheral
                                `ETY                    :       begin
                                                state = sTc;
 
                                                entypeEn = 1;           tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
 
 
                                                aluOpcode = 0;           branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `RST                    :       begin
                                                state = sTc;
 
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 1;          tcPresetEn = 0;  tcLoadEn = 0;
 
 
                                                aluOpcode = 0;           branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `LdTC                   :       begin
                                                state = sTc;
 
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 1;
 
                                                accMuxSel = `accMuxSelTcLoad;           accEn = 1;      // loading TC status data
 
                                                aluOpcode = 0;           branch = 0;                      op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `LdACC                  :       begin
                                                state = sTc;
 
                                                entypeEn = 0;            tcAccRead = 1;  tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
 
                                                accMuxSel = `accMuxSelTcAcc;            accEn = 1;      // loading TC ACC data
 
                                                aluOpcode = 0;           branch = 0;              op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef UART_peripheral
                                `UARTrd                 :       begin
                                                state = sUart;
 
                                                uartRead = 1;           uartWrite = 0;
 
                                                accMuxSel = `accMuxSelUart;             accEn = 1;      // loading UART data
 
                                                aluOpcode = 0;           branch = 0;op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef UART_peripheral
                                `UARTwr                 :       begin
                                                state = sUart;
 
                                                uartRead = 0;            uartWrite = 1;
 
                                                aluOpcode = 0;           branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef SPI_peripheral
                                `SPIxFER                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1;             spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
 
 
                                                aluOpcode = 0;           branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIstat                        :       begin
                                                state = sSpi;
 
                                                sconEn = 0;              spiStatRead = 1;        spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
 
 
                                                aluOpcode = 0;           branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIwBUF                        :       begin
                                                state = sSpi;
 
                                                sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 1;        spiBufShift = 0;
 
 
                                                aluOpcode = 0;           branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIrBUF                        :       begin
                                                state = sSpi;
 
                                                sconEn = 0;              spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;
 
 
                                                aluOpcode = 0;           branch = 0;              accMuxSel = 0;           accEn = 0;       op2MuxSel = 0;
                                                bitRamEn = 0;    bitRamRw = 1;   byteRamEn = 0;           byteRamRw = 1;          inputRead = 0;           outputRw = 1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                end
                                `endif
 
                                default         :       begin
 
                                $write ("       unknown/unused instruction op-code encountered by control unit  ");
                                $stop;
                                end
                                endcase // end  case (instOpCode)
 
 
 
                        end     // end case (s)
 
 
                        sBr             :       begin
                                                        branch = 0;
                                                        state = s;
                                                        end             // end case sBr
 
 
                        sLd             :       begin
                                                        accEn = 0;
                                                        state = s;
                                                        end             // end case sLd
 
                        sSt             :       begin
                                                        bitRamRw = 1;   byteRamRw = 1; outputRw = 1;
                                                        state = s;
                                                        end
 
                        sAlu            :       begin
                                                        accEn = 1;
                                                        accMuxSel = `accMuxSelAluOut;
                                                        state = s;
                                                        end
 
                        `ifdef timerAndCounter_peripheral
                        sTc             :       begin
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                        state = s;
                                                        end
                        `endif
 
                        `ifdef UART_peripheral
                        sUart           :       begin
                                                        uartRead = 0;            uartWrite = 0;
                                                        state = s;
                                                        end
                        `endif
 
                        `ifdef SPI_peripheral
                        sSpi            :       begin
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                        state = s;
                                                        end
                        `endif
 
                        default         :       begin
                        $write ("       control unit FSM in unknown state.      ");
                        end
                        endcase // end  case (state)
                end     // end else part (outermost)
 
 
 
        end     // end always
 
 
endmodule

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [controlUnit.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6	5	maheshpalv	`module controlUnit (clk, reset, instOpCode, acc0, iomemCode,`
7	3	maheshpalv	`branch,`
8			`accMuxSel, accEn, op2MuxSel, aluOpcode,`
9			`bitRamEn, bitRamRw, byteRamEn, byteRamRw,`
10			`inputRead, outputRw`
11
12			`ifdef timerAndCounter_peripheral
13			`, entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn`
14			`endif
15
16			`ifdef UART_peripheral
17			`, uartRead, uartWrite`
18			`endif
19
20			`ifdef SPI_peripheral
21			`, sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift`
22			`endif
23
24			`);`
25
26
27			`input clk, reset;`
28			input [`instOpCodeLen-1:0] instOpCode;
29			`input acc0;`
30			`input [1:0] iomemCode;`
31
32			`output branch;`
33			output [`accMuxSelLen-1:0] accMuxSel;
34			`output accEn;`
35			output [`op2MuxSelLen-1:0] op2MuxSel;
36			output [`aluOpcodeLen-1:0] aluOpcode;
37			`output bitRamEn, bitRamRw, byteRamEn, byteRamRw;`
38			`output inputRead, outputRw;`
39
40			`ifdef timerAndCounter_peripheral
41			`output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;`
42	5	maheshpalv	`endif
43	3	maheshpalv
44			`ifdef UART_peripheral
45			`output uartRead, uartWrite;`
46			`endif
47
48			`ifdef SPI_peripheral
49			`output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;`
50			`endif
51	5	maheshpalv
52			`reg branch;`
53			reg [`accMuxSelLen-1:0] accMuxSel;
54			`reg accEn;`
55			reg [`op2MuxSelLen-1:0] op2MuxSel;
56			reg [`aluOpcodeLen-1:0] aluOpcode;
57			`reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;`
58			`reg inputRead, outputRw;`
59
60			`ifdef timerAndCounter_peripheral
61			`reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;`
62			`endif
63
64			`ifdef UART_peripheral
65			`reg uartRead, uartWrite;`
66			`endif
67	3	maheshpalv
68	5	maheshpalv	`ifdef SPI_peripheral
69			`reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;`
70			`endif
71
72			reg [`cuStateLen-1:0] state;
73
74			`// control unit FSM states:`
75
76			parameter s = `cuStateLen'b0;
77			parameter sTc = `cuStateLen'b1;
78			parameter sBr = `cuStateLen'b10;
79			parameter sLd = `cuStateLen'b11;
80			parameter sSt = `cuStateLen'b100;
81			parameter sUart = `cuStateLen'b101;
82			parameter sSpi = `cuStateLen'b110;
83			parameter sAlu = `cuStateLen'b111;
84
85
86
87
88			`always @ (negedge clk)`
89			`begin`
90
91
92			`if (reset)`
93			`begin`
94			`state = s;`
95
96			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluOpcode = 0; bitRamEn = 0;`
97			`bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
98
99			`ifdef timeAndCounter_peripheral
100			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
101			`endif
102
103			`ifdef UART_peripheral
104			`uartRead = 0; uartWrite = 0;`
105			`endif
106
107			`ifdef SPI_peripheral
108			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
109			`endif
110			`end`
111
112			`else`
113			`begin`
114
115			`// execution unit control signals`
116
117			`case (state)`
118
119			`s : begin`
120
121	3	maheshpalv
122	5	maheshpalv	`case (instOpCode)`
123
124			`END : begin
125
126			`state = sBr;`
127
128			`branch = 1; // branch to some address . . .`
129			`accMuxSel = 0;`
130			`accEn = 0;`
131			`op2MuxSel = 0;`
132			`aluOpcode = 0;`
133			`bitRamEn = 0;`
134			`bitRamRw = 1;`
135			`byteRamEn = 0;`
136			`byteRamRw = 1;`
137			`inputRead = 0;`
138			`outputRw = 1;`
139
140			`ifdef timeAndCounter_peripheral
141			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
142			`endif
143
144			`ifdef UART_peripheral
145			`uartRead = 0; uartWrite = 0;`
146			`endif
147
148			`ifdef SPI_peripheral
149			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0;`
150			`spiBufShift = 0;`
151			`endif
152
153			`end // end case END`
154	3	maheshpalv
155
156	5	maheshpalv
157			`JMP : begin
158
159			`state = sBr;`
160
161			`branch = 1; // branch to some address . . .`
162			`accMuxSel = 0;`
163			`accEn = 0;`
164			`op2MuxSel = 0;`
165			`aluOpcode = 0;`
166			`bitRamEn = 0;`
167			`bitRamRw = 1;`
168			`byteRamEn = 0;`
169			`byteRamRw = 1;`
170			`inputRead = 0;`
171			`outputRw = 1;`
172
173			`ifdef timeAndCounter_peripheral
174			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
175			`endif
176
177			`ifdef UART_peripheral
178			`uartRead = 0; uartWrite = 0;`
179			`endif
180
181			`ifdef SPI_peripheral
182			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
183			`endif
184
185			`end // end case JMP`
186
187
188
189			`Ld : begin
190			`// load thr. op2 MUX and alu.... enable acc in next cycle`
191			`state = sLd;`
192
193			`branch = 0;`
194			`accMuxSel = 0;`
195			`accEn = 0;`
196
197			`case (iomemCode)`
198			2'b00 : op2MuxSel = `op2MuxSelInput;
199			2'b01 : op2MuxSel = `op2MuxSelOutput;
200			2'b10 : op2MuxSel = `op2MuxSelBitRam;
201			2'b11 : op2MuxSel = `op2MuxSelByteRam;
202			default: op2MuxSel = `op2MuxSelInput;
203			`endcase`
204
205			aluOpcode = `LD_data;
206
207			`bitRamEn = 0;`
208			`bitRamRw = 1;`
209			`byteRamEn = 0;`
210			`byteRamRw = 1;`
211			`inputRead = 0;`
212			`outputRw = 1;`
213
214			`ifdef timeAndCounter_peripheral
215			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
216			`endif
217
218			`ifdef UART_peripheral
219			`uartRead = 0; uartWrite = 0;`
220			`endif
221
222			`ifdef SPI_peripheral
223			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
224			`endif
225
226			`end // end case Ld`
227
228
229
230
231			`Ldi : begin
232			`state = sAlu;`
233
234			`branch = 0;`
235			accMuxSel = `accMuxSelImmData; // select imm data thr mux
236			`accEn = 1; // acc enabled`
237			`op2MuxSel = 0;`
238			`aluOpcode = 0;`
239			`bitRamEn = 0;`
240			`bitRamRw = 1;`
241			`byteRamEn = 0;`
242			`byteRamRw = 1;`
243			`inputRead = 0;`
244			`outputRw = 1;`
245
246			`ifdef timeAndCounter_peripheral
247			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
248			`endif
249
250			`ifdef UART_peripheral
251			`uartRead = 0; uartWrite = 0;`
252			`endif
253
254			`ifdef SPI_peripheral
255			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
256			`endif
257
258			`end // end case Ldi`
259
260
261
262			`ST : begin
263			`state = sSt;`
264
265			`branch = 0;`
266			`accMuxSel = 0;`
267			`accEn = 0;`
268			`op2MuxSel = 0;`
269			`aluOpcode = 0;`
270			`bitRamRw = 0;`
271			`byteRamRw = 0;`
272			`inputRead = 0;`
273
274			`case (iomemCode)`
275			`2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; end`
276			`2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; end`
277			`2'b11 : begin bitRamRw = 1; byteRamRw = 1; outputRw = 0; end`
278			`default: begin bitRamRw = 1; byteRamRw = 1; outputRw = 1; end`
279			`endcase`
280
281			`ifdef timeAndCounter_peripheral
282			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
283			`endif
284
285			`ifdef UART_peripheral
286			`uartRead = 0; uartWrite = 0;`
287			`endif
288
289			`ifdef SPI_peripheral
290			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
291			`endif
292
293			`end`
294
295
296
297			`ADD : begin
298			`state = sAlu;`
299			aluOpcode = `ADD_alu;
300
301			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
302			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
303
304			`ifdef timeAndCounter_peripheral
305			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
306			`endif
307
308			`ifdef UART_peripheral
309			`uartRead = 0; uartWrite = 0;`
310			`endif
311
312			`ifdef SPI_peripheral
313			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
314			`endif
315
316			`end`
317
318
319			`SUB : begin
320			`state = sAlu;`
321			aluOpcode = `SUB_alu;
322
323			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
324			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
325
326			`ifdef timeAndCounter_peripheral
327			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
328			`endif
329
330			`ifdef UART_peripheral
331			`uartRead = 0; uartWrite = 0;`
332			`endif
333
334			`ifdef SPI_peripheral
335			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
336			`endif
337
338			`end`
339
340			`// MUL & DIV are not implemented`
341
342
343
344			`AND : begin
345			`state = sAlu;`
346			aluOpcode = `AND_alu;
347
348			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
349			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
350
351			`ifdef timeAndCounter_peripheral
352			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
353			`endif
354
355			`ifdef UART_peripheral
356			`uartRead = 0; uartWrite = 0;`
357			`endif
358
359			`ifdef SPI_peripheral
360			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
361			`endif
362
363			`end`
364
365
366
367			`OR : begin
368			`state = sAlu;`
369			aluOpcode = `OR_alu;
370
371			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
372			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
373
374			`ifdef timeAndCounter_peripheral
375			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
376			`endif
377
378			`ifdef UART_peripheral
379			`uartRead = 0; uartWrite = 0;`
380			`endif
381
382			`ifdef SPI_peripheral
383			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
384			`endif
385
386			`end`
387
388
389
390			`XOR : begin
391			`state = sAlu;`
392			aluOpcode = `XOR_alu;
393
394			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
395			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
396
397			`ifdef timeAndCounter_peripheral
398			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
399			`endif
400
401			`ifdef UART_peripheral
402			`uartRead = 0; uartWrite = 0;`
403			`endif
404
405			`ifdef SPI_peripheral
406			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
407			`endif
408
409			`end`
410
411
412
413			`GrT : begin
414			`state = sAlu;`
415			aluOpcode = `GT_alu;
416
417			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
418			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
419
420			`ifdef timeAndCounter_peripheral
421			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
422			`endif
423
424			`ifdef UART_peripheral
425			`uartRead = 0; uartWrite = 0;`
426			`endif
427
428			`ifdef SPI_peripheral
429			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
430			`endif
431
432			`end`
433
434
435
436
437
438			`GE : begin
439			`state = sAlu;`
440			aluOpcode = `GE_alu;
441
442			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
443			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
444
445			`ifdef timeAndCounter_peripheral
446			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
447			`endif
448
449			`ifdef UART_peripheral
450			`uartRead = 0; uartWrite = 0;`
451			`endif
452
453			`ifdef SPI_peripheral
454			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
455			`endif
456
457			`end`
458
459
460
461
462
463			`EQ : begin
464			`state = sAlu;`
465			aluOpcode = `EQ_alu;
466
467			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
468			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
469
470			`ifdef timeAndCounter_peripheral
471			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
472			`endif
473
474			`ifdef UART_peripheral
475			`uartRead = 0; uartWrite = 0;`
476			`endif
477
478			`ifdef SPI_peripheral
479			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
480			`endif
481
482			`end`
483
484
485
486
487
488			`LE : begin
489			`state = sAlu;`
490			aluOpcode = `LE_alu;
491
492			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
493			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
494
495			`ifdef timeAndCounter_peripheral
496			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
497			`endif
498
499			`ifdef UART_peripheral
500			`uartRead = 0; uartWrite = 0;`
501			`endif
502
503			`ifdef SPI_peripheral
504			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
505			`endif
506
507			`end`
508
509
510
511
512
513			`LT : begin
514			`state = sAlu;`
515			aluOpcode = `LT_alu;
516
517			`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
518			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
519
520			`ifdef timeAndCounter_peripheral
521			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
522			`endif
523
524			`ifdef UART_peripheral
525			`uartRead = 0; uartWrite = 0;`
526			`endif
527
528			`ifdef SPI_peripheral
529			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
530			`endif
531
532			`end`
533
534
535			`ifdef timeAndCounter_peripheral
536			`PRE : begin
537			`state = sTc;`
538
539			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 1; tcLoadEn = 0;`
540
541
542			`aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
543			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
544
545
546			`ifdef UART_peripheral
547			`uartRead = 0; uartWrite = 0;`
548			`endif
549
550			`ifdef SPI_peripheral
551			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
552			`endif
553			`end`
554			`endif
555
556
557			`ifdef timeAndCounter_peripheral
558			`ETY : begin
559			`state = sTc;`
560
561			`entypeEn = 1; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
562
563
564			`aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
565			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
566
567
568			`ifdef UART_peripheral
569			`uartRead = 0; uartWrite = 0;`
570			`endif
571
572			`ifdef SPI_peripheral
573			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
574			`endif
575			`end`
576			`endif
577
578
579
580			`ifdef timeAndCounter_peripheral
581			`RST : begin
582			`state = sTc;`
583
584			`entypeEn = 0; tcAccRead = 0; tcResetEn = 1; tcPresetEn = 0; tcLoadEn = 0;`
585
586
587			`aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
588			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
589
590
591			`ifdef UART_peripheral
592			`uartRead = 0; uartWrite = 0;`
593			`endif
594
595			`ifdef SPI_peripheral
596			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
597			`endif
598			`end`
599			`endif
600
601
602
603			`ifdef timeAndCounter_peripheral
604			`LdTC : begin
605			`state = sTc;`
606
607			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 1;`
608
609			accMuxSel = `accMuxSelTcLoad; accEn = 1; // loading TC status data
610
611			`aluOpcode = 0; branch = 0; op2MuxSel = 0;`
612			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
613
614
615			`ifdef UART_peripheral
616			`uartRead = 0; uartWrite = 0;`
617			`endif
618
619			`ifdef SPI_peripheral
620			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
621			`endif
622			`end`
623			`endif
624
625
626
627			`ifdef timeAndCounter_peripheral
628			`LdACC : begin
629			`state = sTc;`
630
631			`entypeEn = 0; tcAccRead = 1; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
632
633			accMuxSel = `accMuxSelTcAcc; accEn = 1; // loading TC ACC data
634
635			`aluOpcode = 0; branch = 0; op2MuxSel = 0;`
636			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
637
638
639			`ifdef UART_peripheral
640			`uartRead = 0; uartWrite = 0;`
641			`endif
642
643			`ifdef SPI_peripheral
644			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
645			`endif
646			`end`
647			`endif
648
649
650
651
652			`ifdef UART_peripheral
653			`UARTrd : begin
654			`state = sUart;`
655
656			`uartRead = 1; uartWrite = 0;`
657
658			accMuxSel = `accMuxSelUart; accEn = 1; // loading UART data
659
660			`aluOpcode = 0; branch = 0;op2MuxSel = 0;`
661			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
662
663			`ifdef timerAndCounter_peripheral
664			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
665			`endif
666
667
668			`ifdef SPI_peripheral
669			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
670			`endif
671			`end`
672			`endif
673
674
675
676
677			`ifdef UART_peripheral
678			`UARTwr : begin
679			`state = sUart;`
680
681			`uartRead = 0; uartWrite = 1;`
682
683			`aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
684			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
685
686			`ifdef timerAndCounter_peripheral
687			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
688			`endif
689
690
691			`ifdef SPI_peripheral
692			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
693			`endif
694			`end`
695			`endif
696
697
698
699
700			`ifdef SPI_peripheral
701			`SPIxFER : begin
702			`state = sSpi;`
703
704			`sconEn = 1; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
705
706
707			`aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
708			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
709
710			`ifdef timerAndCounter_peripheral
711			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
712			`endif
713
714			`ifdef UART_peripheral
715			`uartRead = 0; uartWrite = 0;`
716			`endif
717
718			`end`
719			`endif
720
721
722
723			`ifdef SPI_peripheral
724			`SPIstat : begin
725			`state = sSpi;`
726
727			`sconEn = 0; spiStatRead = 1; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
728
729
730			`aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
731			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
732
733			`ifdef timerAndCounter_peripheral
734			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
735			`endif
736
737			`ifdef UART_peripheral
738			`uartRead = 0; uartWrite = 0;`
739			`endif
740
741			`end`
742			`endif
743
744
745
746			`ifdef SPI_peripheral
747			`SPIwBUF : begin
748			`state = sSpi;`
749
750			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 1; spiBufShift = 0;`
751
752
753			`aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
754			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
755
756			`ifdef timerAndCounter_peripheral
757			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
758			`endif
759
760			`ifdef UART_peripheral
761			`uartRead = 0; uartWrite = 0;`
762			`endif
763
764			`end`
765			`endif
766
767
768
769			`ifdef SPI_peripheral
770			`SPIrBUF : begin
771			`state = sSpi;`
772
773			`sconEn = 0; spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;`
774
775
776			`aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;`
777			`bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
778
779			`ifdef timerAndCounter_peripheral
780			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
781			`endif
782
783			`ifdef UART_peripheral
784			`uartRead = 0; uartWrite = 0;`
785			`endif
786
787			`end`
788			`endif
789
790			`default : begin`
791
792			`$write (" unknown/unused instruction op-code encountered by control unit ");`
793			`$stop;`
794			`end`
795			`endcase // end case (instOpCode)`
796
797
798
799			`end // end case (s)`
800
801
802			`sBr : begin`
803			`branch = 0;`
804			`state = s;`
805			`end // end case sBr`
806
807
808			`sLd : begin`
809			`accEn = 0;`
810			`state = s;`
811			`end // end case sLd`
812
813			`sSt : begin`
814			`bitRamRw = 1; byteRamRw = 1; outputRw = 1;`
815			`state = s;`
816			`end`
817
818			`sAlu : begin`
819			`accEn = 1;`
820			accMuxSel = `accMuxSelAluOut;
821			`state = s;`
822			`end`
823
824			`ifdef timerAndCounter_peripheral
825			`sTc : begin`
826			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
827			`state = s;`
828			`end`
829			`endif
830
831			`ifdef UART_peripheral
832			`sUart : begin`
833			`uartRead = 0; uartWrite = 0;`
834			`state = s;`
835			`end`
836			`endif
837
838			`ifdef SPI_peripheral
839			`sSpi : begin`
840			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
841			`state = s;`
842			`end`
843			`endif
844
845			`default : begin`
846			`$write (" control unit FSM in unknown state. ");`
847			`end`
848			`endcase // end case (state)`
849			`end // end else part (outermost)`
850
851
852
853			`end // end always`
854
855
856	3	maheshpalv	`endmodule`