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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [controlUnit.v] - Blame information for rev 7

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`include "timescale.v"
`include "defines.v"
 
 
module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
                                                        branch,
                                                        accMuxSel, accEn, op2MuxSel, aluEn, aluOpcode,
                                                        bitRamEn, bitRamRw, byteRamEn, byteRamRw,
                                                        inputRead, outputRw
 
                                                        `ifdef timerAndCounter_peripheral
                                                                , entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn
                                                        `endif
 
                                                        `ifdef UART_peripheral
                                                                , uartRead, uartWrite
                                                        `endif
 
                                                        `ifdef SPI_peripheral
                                                                , sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift
                                                        `endif
 
                                                        );
 
 
        input clk, reset;
        input [`instOpCodeLen-1:0] instOpCode;
        input acc0;
        input [1:0] iomemCode;
 
        output branch;
        output [`accMuxSelLen-1:0]       accMuxSel;
        output accEn;
        output [`op2MuxSelLen-1:0]       op2MuxSel;
        output aluEn;
        output [`aluOpcodeLen-1:0] aluOpcode;
        output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
        output inputRead, outputRw;
 
        `ifdef timerAndCounter_peripheral
        output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
        `endif
 
        `ifdef UART_peripheral
        output uartRead, uartWrite;
        `endif
 
        `ifdef SPI_peripheral
        output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
        `endif
 
        reg branch;
        reg [`accMuxSelLen-1:0]  accMuxSel;
        reg accEn;
        reg [`op2MuxSelLen-1:0]  op2MuxSel;
        reg aluEn;
        reg [`aluOpcodeLen-1:0] aluOpcode;
        reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
        reg inputRead, outputRw;
 
        `ifdef timerAndCounter_peripheral
        reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
        `endif
 
        `ifdef UART_peripheral
        reg uartRead, uartWrite;
        `endif
 
        `ifdef SPI_peripheral
        reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
        `endif
 
        reg [`cuStateLen-1:0] state;
 
        // control unit FSM states:
 
        parameter       s               = `cuStateLen'b0;
        parameter       sTc     = `cuStateLen'b1;
        parameter       sBr     = `cuStateLen'b10;
        parameter       sLd     = `cuStateLen'b11;
        parameter       sSt     = `cuStateLen'b100;
        parameter       sUart   = `cuStateLen'b101;
        parameter       sSpi    = `cuStateLen'b110;
        parameter       sAlu    = `cuStateLen'b111;
 
 
 
 
        always @ (negedge clk)
        begin
 
 
                if (reset)
                begin
                        state = s;
 
                        branch = 0;      accMuxSel = 0;   accEn = 0;       op2MuxSel = 0;   aluEn = 0; aluOpcode = 0; bitRamEn = 0;
                        bitRamRw = 1;   byteRamEn = 0;   byteRamRw = 1;  inputRead = 0;   outputRw = 1;
 
                        `ifdef timeAndCounter_peripheral
                                entypeEn = 0;    tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                        `endif
 
                        `ifdef UART_peripheral
                                uartRead = 0;    uartWrite = 0;
                        `endif
 
                        `ifdef SPI_peripheral
                                sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                        `endif
                end
 
                else
                begin
 
                        // execution unit control signals
 
                        case (state)
 
                        s               :               begin
 
 
                                case (instOpCode)
 
                                `END                    :       begin
 
                                                state = sBr;
 
                                                branch = 1;                     // branch to some address . . .
                                                accMuxSel = 0;
                                                accEn = 0;
                                                op2MuxSel = 0;
                                                aluEn = 0;
                                                aluOpcode = 0;
                                                bitRamEn = 0;
                                                bitRamRw = 1;
                                                byteRamEn = 0;
                                                byteRamRw = 1;
                                                inputRead = 0;
                                                outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0;
                                                        spiBufShift = 0;
                                                `endif
 
                                end     // end case END
 
 
 
                                `JMP                    :       begin
 
                                                state = sBr;
 
                                                if (acc0)
                                                        branch = 1;                     // branch to some address . . .
                                                else
                                                        branch = 0;
                                                accMuxSel = 0;
                                                accEn = 0;
                                                op2MuxSel = 0;
                                                aluEn = 0;
                                                aluOpcode = 0;
                                                bitRamEn = 0;
                                                bitRamRw = 1;
                                                byteRamEn = 0;
                                                byteRamRw = 1;
                                                inputRead = 0;
                                                outputRw = 1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 0;            tcAccRead = 0;   tcResetEn = 0;           tcPresetEn = 0;  tcLoadEn = 0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 0;            uartWrite = 0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 0;              spiStatRead = 0; spiBufRead = 0;  spiBufWrite = 0; spiBufShift = 0;
                                                `endif
 
                                end     // end case JMP
 
 
 
                                `Ld                     :       begin
                                // load thr. op2 MUX and alu.... enable acc in next cycle
                                                state = sLd;
 
                                                branch = 0;
                                                accMuxSel = 0;
                                                accEn = 0;
 
                                                        case (iomemCode)
                                                        2'b00   :       op2MuxSel = `op2MuxSelInput;
                                                        2'b01   :       op2MuxSel = `op2MuxSelOutput;
                                                        2'b10   :       op2MuxSel = `op2MuxSelBitRam;
                                                        2'b11   :       op2MuxSel = `op2MuxSelByteRam;
                                                        default:        op2MuxSel = `op2MuxSelInput;
                                                        endcase
                                                        aluEn = 1'b1;
                                                        aluOpcode = `LD_data;
 
                                                bitRamEn = 1'b1;
                                                bitRamRw = 1'b1;
                                                byteRamEn = 1'b1;
                                                byteRamRw = 1'b1;
                                                inputRead = 1'b1;
                                                outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end     // end case Ld
 
 
 
 
                                `Ldi                    :       begin
                                                state = sAlu;
 
                                                branch = 1'b0;
                                                        accMuxSel = `accMuxSelImmData;  // select imm data thr mux
                                                        accEn = 1'b1;           // acc enabled
                                                op2MuxSel = 1'b0;
                                                aluOpcode = 1'b0;
                                                aluEn = 1'b0;
                                                bitRamEn = 1'b0;
                                                bitRamRw = 1'b1;
                                                byteRamEn = 1'b0;
                                                byteRamRw = 1'b1;
                                                inputRead = 1'b0;
                                                outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end             // end case Ldi
 
 
 
                                `ST                     :       begin
                                                state = sSt;
 
                                                branch = 1'b0;
                                                accMuxSel = 1'b0;
                                                accEn = 1'b0;
                                                op2MuxSel = 1'b0;
                                                aluEn = 1'b0;
                                                aluOpcode = 1'b0;
                                                inputRead = 1'b0;
 
                                                        case (iomemCode)
                                                        2'b01   :       begin   bitRamRw = 1'b0;        byteRamRw = 1'b1;       outputRw = 1'b1; bitRamEn = 1'b1;       byteRamEn = 1'b1;       end
                                                        2'b10   :       begin   bitRamRw = 1'b1;        byteRamRw = 1'b0;       outputRw = 1'b1; bitRamEn = 1'b1;       byteRamEn = 1'b1;       end
                                                        2'b11   :       begin   bitRamRw = 1'b1;        byteRamRw = 1'b1;       outputRw = 1'b0; end
                                                        default:        begin   bitRamRw = 1'b1;        byteRamRw = 1'b1;       outputRw = 1'b1;        end
                                                        endcase
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
                                `ADD                    :       begin
                                                state = sAlu;
                                                aluOpcode = `ADD_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
                                `SUB                    :       begin
                                                state = sAlu;
                                                aluOpcode = `SUB_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
                                // MUL & DIV are not implemented
 
 
 
                                `AND                    :       begin
                                                state = sAlu;
                                                aluOpcode = `AND_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
                                `OR                     :       begin
                                                state = sAlu;
                                                aluOpcode = `OR_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
                                `XOR                    :       begin
                                                state = sAlu;
                                                aluOpcode = `XOR_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
                                `GrT                    :       begin
                                                state = sAlu;
                                                aluOpcode = `GT_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
 
 
                                `GE                     :       begin
                                                state = sAlu;
                                                aluOpcode = `GE_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
 
 
                                `EQ                     :       begin
                                                state = sAlu;
                                                aluOpcode = `EQ_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
 
 
                                `LE                     :       begin
                                                state = sAlu;
                                                aluOpcode = `LE_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
 
 
 
                                `LT                     :       begin
                                                state = sAlu;
                                                aluOpcode = `LT_alu;
                                                aluEn = 1'b1;
                                                branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timeAndCounter_peripheral
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
 
                                end
 
 
                                `ifdef timeAndCounter_peripheral
                                `PRE                    :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b1;      tcLoadEn = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
                                `ifdef timeAndCounter_peripheral
                                `ETY                    :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b1;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `RST                    :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b1;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `LdTC                   :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b1;
 
                                                accMuxSel = `accMuxSelTcLoad;           accEn = 1'b1;   // loading TC status data
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;                  op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef timeAndCounter_peripheral
                                `LdACC                  :       begin
                                                state = sTc;
 
                                                entypeEn = 1'b0;                tcAccRead = 1'b1;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
 
                                                accMuxSel = `accMuxSelTcAcc;            accEn = 1'b1;   // loading TC ACC data
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
 
                                                `ifdef UART_peripheral
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef UART_peripheral
                                `UARTrd                 :       begin
                                                state = sUart;
 
                                                uartRead = 1'b1;                uartWrite = 1'b0;
 
                                                accMuxSel = `accMuxSelUartData;         accEn = 1'b1;   // loading UART data
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
                                `ifdef UART_peripheral
                                `UARTstat                       :       begin
                                                state = sUart;
 
                                                uartRead = 1'b0;                uartWrite = 1'b0;
 
                                                accMuxSel = `accMuxSelUartStat;         accEn = 1'b1;   // loading UART status
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef UART_peripheral
                                `UARTwr                 :       begin
                                                state = sUart;
 
                                                uartRead = 1'b0;                uartWrite = 1'b1;
 
                                                aluEn = 1'b0;   aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
 
                                                `ifdef SPI_peripheral
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                `endif
                                end
                                `endif
 
 
 
 
                                `ifdef SPI_peripheral
                                `SPIxFER                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1'b1;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIstat                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1'b0;          spiStatRead = 1'b1;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIwBUF                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b1;     spiBufShift = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                end
                                `endif
 
 
 
                                `ifdef SPI_peripheral
                                `SPIrBUF                        :       begin
                                                state = sSpi;
 
                                                sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b1;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
 
 
                                                aluEn = 1'b0;   aluOpcode = 1'b0;               branch = 1'b0;          accMuxSel = 1'b0;               accEn = 1'b0;   op2MuxSel = 1'b0;
                                                bitRamEn = 1'b0;        bitRamRw = 1'b1;        byteRamEn = 1'b0;               byteRamRw = 1'b1;               inputRead = 1'b0;               outputRw = 1'b1;
 
                                                `ifdef timerAndCounter_peripheral
                                                entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                `endif
 
                                                `ifdef UART_peripheral
                                                uartRead = 1'b0;                uartWrite = 1'b0;
                                                `endif
 
                                end
                                `endif
 
                                default         :       begin
 
                                $write ("       unknown/unused instruction op-code encountered by control unit  ");
                                $stop;
                                end
                                endcase // end  case (instOpCode)
 
 
 
                        end     // end case (s)
 
 
                        sBr             :       begin
                                                        branch = 1'b0;
                                                        state = s;
                                                        end             // end case sBr
 
 
                        sLd             :       begin
                                                        aluEn = 1'b0;
                                                        accEn = 1'b1;
                                                        accMuxSel = `accMuxSelAluOut;
                                                        state = s;
                                                        end             // end case sLd
 
                        sSt             :       begin
                                                        bitRamRw = 1'b1;        byteRamRw = 1'b1; outputRw = 1'b1;
                                                        state = s;
                                                        end
 
                        sAlu            :       begin
                                                        aluEn = 1'b0;
                                                        accEn = 1'b1;
                                                        accMuxSel = `accMuxSelAluOut;
                                                        state = s;
                                                        end
 
                        `ifdef timerAndCounter_peripheral
                        sTc             :       begin
                                                        entypeEn = 1'b0;                tcAccRead = 1'b0;       tcResetEn = 1'b0;               tcPresetEn = 1'b0;      tcLoadEn = 1'b0;
                                                        state = s;
                                                        end
                        `endif
 
                        `ifdef UART_peripheral
                        sUart           :       begin
                                                        uartRead = 1'b0;                uartWrite = 1'b0;
                                                        state = s;
                                                        end
                        `endif
 
                        `ifdef SPI_peripheral
                        sSpi            :       begin
                                                        sconEn = 1'b0;          spiStatRead = 1'b0;     spiBufRead = 1'b0;      spiBufWrite = 1'b0;     spiBufShift = 1'b0;
                                                        state = s;
                                                        end
                        `endif
 
                        default         :       begin
                        $write ("       control unit FSM in unknown state.      ");
                        end
                        endcase // end  case (state)
                end     // end else part (outermost)
 
 
 
        end     // end always
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6	5	maheshpalv	`module controlUnit (clk, reset, instOpCode, acc0, iomemCode,`
7	3	maheshpalv	`branch,`
8	6	maheshpalv	`accMuxSel, accEn, op2MuxSel, aluEn, aluOpcode,`
9	3	maheshpalv	`bitRamEn, bitRamRw, byteRamEn, byteRamRw,`
10			`inputRead, outputRw`
11
12			`ifdef timerAndCounter_peripheral
13			`, entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn`
14			`endif
15
16			`ifdef UART_peripheral
17			`, uartRead, uartWrite`
18			`endif
19
20			`ifdef SPI_peripheral
21			`, sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift`
22			`endif
23
24			`);`
25
26
27			`input clk, reset;`
28			input [`instOpCodeLen-1:0] instOpCode;
29			`input acc0;`
30			`input [1:0] iomemCode;`
31
32			`output branch;`
33			output [`accMuxSelLen-1:0] accMuxSel;
34			`output accEn;`
35			output [`op2MuxSelLen-1:0] op2MuxSel;
36	6	maheshpalv	`output aluEn;`
37	3	maheshpalv	output [`aluOpcodeLen-1:0] aluOpcode;
38			`output bitRamEn, bitRamRw, byteRamEn, byteRamRw;`
39			`output inputRead, outputRw;`
40
41			`ifdef timerAndCounter_peripheral
42			`output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;`
43	5	maheshpalv	`endif
44	3	maheshpalv
45			`ifdef UART_peripheral
46			`output uartRead, uartWrite;`
47			`endif
48
49			`ifdef SPI_peripheral
50			`output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;`
51			`endif
52	5	maheshpalv
53			`reg branch;`
54			reg [`accMuxSelLen-1:0] accMuxSel;
55			`reg accEn;`
56			reg [`op2MuxSelLen-1:0] op2MuxSel;
57	6	maheshpalv	`reg aluEn;`
58	5	maheshpalv	reg [`aluOpcodeLen-1:0] aluOpcode;
59			`reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;`
60			`reg inputRead, outputRw;`
61
62			`ifdef timerAndCounter_peripheral
63			`reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;`
64			`endif
65
66			`ifdef UART_peripheral
67			`reg uartRead, uartWrite;`
68			`endif
69	3	maheshpalv
70	5	maheshpalv	`ifdef SPI_peripheral
71			`reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;`
72			`endif
73
74			reg [`cuStateLen-1:0] state;
75
76			`// control unit FSM states:`
77
78			parameter s = `cuStateLen'b0;
79			parameter sTc = `cuStateLen'b1;
80			parameter sBr = `cuStateLen'b10;
81			parameter sLd = `cuStateLen'b11;
82			parameter sSt = `cuStateLen'b100;
83			parameter sUart = `cuStateLen'b101;
84			parameter sSpi = `cuStateLen'b110;
85			parameter sAlu = `cuStateLen'b111;
86
87
88
89
90			`always @ (negedge clk)`
91			`begin`
92
93
94			`if (reset)`
95			`begin`
96			`state = s;`
97
98	6	maheshpalv	`branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluEn = 0; aluOpcode = 0; bitRamEn = 0;`
99	5	maheshpalv	`bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;`
100
101			`ifdef timeAndCounter_peripheral
102			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
103			`endif
104
105			`ifdef UART_peripheral
106			`uartRead = 0; uartWrite = 0;`
107			`endif
108
109			`ifdef SPI_peripheral
110			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
111			`endif
112			`end`
113
114			`else`
115			`begin`
116
117			`// execution unit control signals`
118
119			`case (state)`
120
121			`s : begin`
122
123	3	maheshpalv
124	5	maheshpalv	`case (instOpCode)`
125
126			`END : begin
127
128			`state = sBr;`
129
130			`branch = 1; // branch to some address . . .`
131			`accMuxSel = 0;`
132			`accEn = 0;`
133			`op2MuxSel = 0;`
134	6	maheshpalv	`aluEn = 0;`
135	5	maheshpalv	`aluOpcode = 0;`
136			`bitRamEn = 0;`
137			`bitRamRw = 1;`
138			`byteRamEn = 0;`
139			`byteRamRw = 1;`
140			`inputRead = 0;`
141			`outputRw = 1;`
142
143			`ifdef timeAndCounter_peripheral
144			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
145			`endif
146
147			`ifdef UART_peripheral
148			`uartRead = 0; uartWrite = 0;`
149			`endif
150
151			`ifdef SPI_peripheral
152			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0;`
153			`spiBufShift = 0;`
154			`endif
155
156			`end // end case END`
157	3	maheshpalv
158
159	5	maheshpalv
160			`JMP : begin
161
162			`state = sBr;`
163
164	6	maheshpalv	`if (acc0)`
165			`branch = 1; // branch to some address . . .`
166			`else`
167			`branch = 0;`
168	5	maheshpalv	`accMuxSel = 0;`
169			`accEn = 0;`
170			`op2MuxSel = 0;`
171	6	maheshpalv	`aluEn = 0;`
172	5	maheshpalv	`aluOpcode = 0;`
173			`bitRamEn = 0;`
174			`bitRamRw = 1;`
175			`byteRamEn = 0;`
176			`byteRamRw = 1;`
177			`inputRead = 0;`
178			`outputRw = 1;`
179
180			`ifdef timeAndCounter_peripheral
181			`entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;`
182			`endif
183
184			`ifdef UART_peripheral
185			`uartRead = 0; uartWrite = 0;`
186			`endif
187
188			`ifdef SPI_peripheral
189			`sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;`
190			`endif
191
192			`end // end case JMP`
193
194
195
196			`Ld : begin
197			`// load thr. op2 MUX and alu.... enable acc in next cycle`
198			`state = sLd;`
199
200			`branch = 0;`
201			`accMuxSel = 0;`
202			`accEn = 0;`
203
204			`case (iomemCode)`
205			2'b00 : op2MuxSel = `op2MuxSelInput;
206			2'b01 : op2MuxSel = `op2MuxSelOutput;
207			2'b10 : op2MuxSel = `op2MuxSelBitRam;
208			2'b11 : op2MuxSel = `op2MuxSelByteRam;
209			default: op2MuxSel = `op2MuxSelInput;
210			`endcase`
211	7	maheshpalv	`aluEn = 1'b1;`
212	5	maheshpalv	aluOpcode = `LD_data;
213
214	7	maheshpalv	`bitRamEn = 1'b1;`
215			`bitRamRw = 1'b1;`
216			`byteRamEn = 1'b1;`
217			`byteRamRw = 1'b1;`
218			`inputRead = 1'b1;`
219			`outputRw = 1'b1;`
220	5	maheshpalv
221			`ifdef timeAndCounter_peripheral
222	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
223	5	maheshpalv	`endif
224
225			`ifdef UART_peripheral
226	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
227	5	maheshpalv	`endif
228
229			`ifdef SPI_peripheral
230	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
231	5	maheshpalv	`endif
232
233			`end // end case Ld`
234
235
236
237
238			`Ldi : begin
239			`state = sAlu;`
240
241	7	maheshpalv	`branch = 1'b0;`
242	5	maheshpalv	accMuxSel = `accMuxSelImmData; // select imm data thr mux
243	7	maheshpalv	`accEn = 1'b1; // acc enabled`
244			`op2MuxSel = 1'b0;`
245			`aluOpcode = 1'b0;`
246			`aluEn = 1'b0;`
247			`bitRamEn = 1'b0;`
248			`bitRamRw = 1'b1;`
249			`byteRamEn = 1'b0;`
250			`byteRamRw = 1'b1;`
251			`inputRead = 1'b0;`
252			`outputRw = 1'b1;`
253	5	maheshpalv
254			`ifdef timeAndCounter_peripheral
255	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
256	5	maheshpalv	`endif
257
258			`ifdef UART_peripheral
259	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
260	5	maheshpalv	`endif
261
262			`ifdef SPI_peripheral
263	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
264	5	maheshpalv	`endif
265
266			`end // end case Ldi`
267
268
269
270			`ST : begin
271			`state = sSt;`
272
273	7	maheshpalv	`branch = 1'b0;`
274			`accMuxSel = 1'b0;`
275			`accEn = 1'b0;`
276			`op2MuxSel = 1'b0;`
277			`aluEn = 1'b0;`
278			`aluOpcode = 1'b0;`
279			`inputRead = 1'b0;`
280	5	maheshpalv
281			`case (iomemCode)`
282	7	maheshpalv	`2'b01 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end`
283			`2'b10 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end`
284			`2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b0; end`
285			`default: begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1; end`
286	5	maheshpalv	`endcase`
287
288			`ifdef timeAndCounter_peripheral
289	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
290	5	maheshpalv	`endif
291
292			`ifdef UART_peripheral
293	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
294	5	maheshpalv	`endif
295
296			`ifdef SPI_peripheral
297	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
298	5	maheshpalv	`endif
299
300			`end`
301
302
303
304			`ADD : begin
305			`state = sAlu;`
306			aluOpcode = `ADD_alu;
307	7	maheshpalv	`aluEn = 1'b1;`
308			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
309			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
310	5	maheshpalv
311			`ifdef timeAndCounter_peripheral
312	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
313	5	maheshpalv	`endif
314
315			`ifdef UART_peripheral
316	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
317	5	maheshpalv	`endif
318
319			`ifdef SPI_peripheral
320	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
321	5	maheshpalv	`endif
322
323			`end`
324
325
326			`SUB : begin
327			`state = sAlu;`
328			aluOpcode = `SUB_alu;
329	7	maheshpalv	`aluEn = 1'b1;`
330			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
331			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
332	5	maheshpalv
333			`ifdef timeAndCounter_peripheral
334	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
335	5	maheshpalv	`endif
336
337			`ifdef UART_peripheral
338	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
339	5	maheshpalv	`endif
340
341			`ifdef SPI_peripheral
342	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
343	5	maheshpalv	`endif
344
345			`end`
346
347			`// MUL & DIV are not implemented`
348
349
350
351			`AND : begin
352			`state = sAlu;`
353			aluOpcode = `AND_alu;
354	7	maheshpalv	`aluEn = 1'b1;`
355			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
356			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
357	5	maheshpalv
358			`ifdef timeAndCounter_peripheral
359	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
360	5	maheshpalv	`endif
361
362			`ifdef UART_peripheral
363	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
364	5	maheshpalv	`endif
365
366			`ifdef SPI_peripheral
367	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
368	5	maheshpalv	`endif
369
370			`end`
371
372
373
374			`OR : begin
375			`state = sAlu;`
376			aluOpcode = `OR_alu;
377	7	maheshpalv	`aluEn = 1'b1;`
378			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
379			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
380	5	maheshpalv
381			`ifdef timeAndCounter_peripheral
382	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
383	5	maheshpalv	`endif
384
385			`ifdef UART_peripheral
386	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
387	5	maheshpalv	`endif
388
389			`ifdef SPI_peripheral
390	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
391	5	maheshpalv	`endif
392
393			`end`
394
395
396
397			`XOR : begin
398			`state = sAlu;`
399			aluOpcode = `XOR_alu;
400	7	maheshpalv	`aluEn = 1'b1;`
401			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
402			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
403	5	maheshpalv
404			`ifdef timeAndCounter_peripheral
405	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
406	5	maheshpalv	`endif
407
408			`ifdef UART_peripheral
409	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
410	5	maheshpalv	`endif
411
412			`ifdef SPI_peripheral
413	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
414	5	maheshpalv	`endif
415
416			`end`
417
418
419
420			`GrT : begin
421			`state = sAlu;`
422			aluOpcode = `GT_alu;
423	7	maheshpalv	`aluEn = 1'b1;`
424			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
425			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
426	5	maheshpalv
427			`ifdef timeAndCounter_peripheral
428	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
429	5	maheshpalv	`endif
430
431			`ifdef UART_peripheral
432	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
433	5	maheshpalv	`endif
434
435			`ifdef SPI_peripheral
436	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
437	5	maheshpalv	`endif
438
439			`end`
440
441
442
443
444
445			`GE : begin
446			`state = sAlu;`
447			aluOpcode = `GE_alu;
448	7	maheshpalv	`aluEn = 1'b1;`
449			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
450			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
451	5	maheshpalv
452			`ifdef timeAndCounter_peripheral
453	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
454	5	maheshpalv	`endif
455
456			`ifdef UART_peripheral
457	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
458	5	maheshpalv	`endif
459
460			`ifdef SPI_peripheral
461	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
462	5	maheshpalv	`endif
463
464			`end`
465
466
467
468
469
470			`EQ : begin
471			`state = sAlu;`
472			aluOpcode = `EQ_alu;
473	7	maheshpalv	`aluEn = 1'b1;`
474			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
475			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`
476	5	maheshpalv
477			`ifdef timeAndCounter_peripheral
478	7	maheshpalv	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
479	5	maheshpalv	`endif
480
481			`ifdef UART_peripheral
482	7	maheshpalv	`uartRead = 1'b0; uartWrite = 1'b0;`
483	5	maheshpalv	`endif
484
485			`ifdef SPI_peripheral
486	7	maheshpalv	`sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;`
487	5	maheshpalv	`endif
488
489			`end`
490
491
492
493
494
495			`LE : begin
496			`state = sAlu;`
497			aluOpcode = `LE_alu;
498	7	maheshpalv	`aluEn = 1'b1;`
499			`branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;`
500			`bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;`

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