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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [counter_all.v] - Blame information for rev 10

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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
 
module counter (clk, reset, preset, type, DN, CU, CD, ACC);
 
        input clk, reset;
        input [`tcPresetLen-1:0] preset;
        input [`tcTypeLen-1:0] type;
 
        output DN, CU, CD;
        output [`tcAccLen-1:0] ACC;
 
        reg DN = 0, CU = 0, CD = 0;
        reg [`tcAccLen-1:0] ACC = 0;
 
        reg [`tcTypeLen-1:0] CounterType;
        reg [`tcTypeLen-1:0] typeNext;
 
 
        parameter       UpCounter       = `tcTypeLen'b01;
        parameter       DownCounter     = `tcTypeLen'b10;
        parameter       defaultType     = `tcTypeLen'b00;
 
 
 
        always @ (type)
        begin
 
                case (type)
 
                `counterType1   :       begin
                                                                typeNext = UpCounter;
                                                                end
 
                `counterType2   :       begin
                                                                typeNext = DownCounter;
                                                                end
 
                default                 :       begin
                                                                $display ("\ncounter is of undefined type.\n Valid types are Up counter & Down counter");
                                                                end
                endcase
        end
 
 
        always @ (posedge clk or posedge reset)
        begin
 
                if (reset)
                begin
                        $display ("counter module is reset");
                        CounterType = defaultType;
                end
                else
                begin
                        CounterType = typeNext;
                end
        end
 
 
        always @ (posedge clk)
        begin
 
                case (CounterType)
 
                UpCounter       :       begin
                                                                        CD = 0;                  // CD id always 0 for this state
 
                                                                        if (reset)
                                                                        begin
                                                                                ACC = `tcAccLen-1'b0;   // starts at lowest value
                                                                                CU = 0;
                                                                                DN = 0;
                                                                        end
                                                                        else
                                                                        begin
                                                                                ACC = ACC + 1'b1;
                                                                                CU = 1'b1;
                                                                                if (ACC > preset)
                                                                                begin
                                                                                        DN = 1'b1;
                                                                                end
                                                                        end
                                                        end
 
 
 
                DownCounter     :       begin
                                                                        CU = 0;                  // CU id always 0 for this state
 
                                                                        if (reset)
                                                                        begin
                                                                                ACC = `tcAccLen-1'b1;   // starts at highest value
                                                                                CD = 0;
                                                                                DN = 0;
                                                                        end
                                                                        else
                                                                        begin
                                                                                ACC = ACC - 1'b1;
                                                                                CD = 1'b1;
                                                                                if (ACC < preset)
                                                                                begin
                                                                                        DN = 1'b1;
                                                                                end
                                                                        end
                                                        end
 
 
 
                default         :       begin
                                                        $display ("\nerror in counter type      ");
                                                        end
 
                endcase
        end
 
 
endmodule

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40	3	maheshpalv
41			`include "timescale.v"
42			`include "defines.v"
43
44
45	7	maheshpalv	`module counter (clk, reset, preset, type, DN, CU, CD, ACC);`
46
47			`input clk, reset;`
48			input [`tcPresetLen-1:0] preset;
49			input [`tcTypeLen-1:0] type;
50
51			`output DN, CU, CD;`
52			output [`tcAccLen-1:0] ACC;
53
54			`reg DN = 0, CU = 0, CD = 0;`
55			reg [`tcAccLen-1:0] ACC = 0;
56
57			reg [`tcTypeLen-1:0] CounterType;
58			reg [`tcTypeLen-1:0] typeNext;
59
60
61			parameter UpCounter = `tcTypeLen'b01;
62			parameter DownCounter = `tcTypeLen'b10;
63			parameter defaultType = `tcTypeLen'b00;
64
65
66
67			`always @ (type)`
68			`begin`
69
70			`case (type)`
71
72			`counterType1 : begin
73			`typeNext = UpCounter;`
74			`end`
75
76			`counterType2 : begin
77			`typeNext = DownCounter;`
78			`end`
79
80			`default : begin`
81	8	maheshpalv	`$display ("\ncounter is of undefined type.\n Valid types are Up counter & Down counter");`
82	7	maheshpalv	`end`
83			`endcase`
84			`end`
85
86
87			`always @ (posedge clk or posedge reset)`
88			`begin`
89
90			`if (reset)`
91			`begin`
92			`$display ("counter module is reset");`
93			`CounterType = defaultType;`
94			`end`
95			`else`
96			`begin`
97			`CounterType = typeNext;`
98			`end`
99			`end`
100
101
102			`always @ (posedge clk)`
103			`begin`
104
105			`case (CounterType)`
106
107			`UpCounter : begin`
108			`CD = 0; // CD id always 0 for this state`
109
110			`if (reset)`
111			`begin`
112			ACC = `tcAccLen-1'b0; // starts at lowest value
113			`CU = 0;`
114			`DN = 0;`
115			`end`
116			`else`
117			`begin`
118			`ACC = ACC + 1'b1;`
119			`CU = 1'b1;`
120			`if (ACC > preset)`
121			`begin`
122			`DN = 1'b1;`
123			`end`
124			`end`
125			`end`
126
127
128
129			`DownCounter : begin`
130			`CU = 0; // CU id always 0 for this state`
131
132			`if (reset)`
133			`begin`
134			ACC = `tcAccLen-1'b1; // starts at highest value
135			`CD = 0;`
136			`DN = 0;`
137			`end`
138			`else`
139			`begin`
140			`ACC = ACC - 1'b1;`
141			`CD = 1'b1;`
142			`if (ACC < preset)`
143			`begin`
144			`DN = 1'b1;`
145			`end`
146			`end`
147			`end`
148
149
150
151			`default : begin`
152	8	maheshpalv	`$display ("\nerror in counter type ");`
153	7	maheshpalv	`end`
154
155			`endcase`
156			`end`
157
158
159			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [counter_all.v] - Blame information for rev 10