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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [counter_all.v] - Blame information for rev 7

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`include "timescale.v"
`include "defines.v"
 
 
module counter (clk, reset, preset, type, DN, CU, CD, ACC);
 
        input clk, reset;
        input [`tcPresetLen-1:0] preset;
        input [`tcTypeLen-1:0] type;
 
        output DN, CU, CD;
        output [`tcAccLen-1:0] ACC;
 
        reg DN = 0, CU = 0, CD = 0;
        reg [`tcAccLen-1:0] ACC = 0;
 
        reg [`tcTypeLen-1:0] CounterType;
        reg [`tcTypeLen-1:0] typeNext;
 
 
        parameter       UpCounter       = `tcTypeLen'b01;
        parameter       DownCounter     = `tcTypeLen'b10;
        parameter       defaultType     = `tcTypeLen'b00;
 
 
 
        always @ (type)
        begin
 
                case (type)
 
                `counterType1   :       begin
                                                                typeNext = UpCounter;
                                                                end
 
                `counterType2   :       begin
                                                                typeNext = DownCounter;
                                                                end
 
                default                 :       begin
                                                                $display ("counter is of undefined type.\n Valid types are Up counter & Down counter");
                                                                end
                endcase
        end
 
 
        always @ (posedge clk or posedge reset)
        begin
 
                if (reset)
                begin
                        $display ("counter module is reset");
                        CounterType = defaultType;
                end
                else
                begin
                        CounterType = typeNext;
                end
        end
 
 
        always @ (posedge clk)
        begin
 
                case (CounterType)
 
                UpCounter       :       begin
                                                                        CD = 0;                  // CD id always 0 for this state
 
                                                                        if (reset)
                                                                        begin
                                                                                ACC = `tcAccLen-1'b0;   // starts at lowest value
                                                                                CU = 0;
                                                                                DN = 0;
                                                                        end
                                                                        else
                                                                        begin
                                                                                ACC = ACC + 1'b1;
                                                                                CU = 1'b1;
                                                                                if (ACC > preset)
                                                                                begin
                                                                                        DN = 1'b1;
                                                                                end
                                                                        end
                                                        end
 
 
 
                DownCounter     :       begin
                                                                        CU = 0;                  // CU id always 0 for this state
 
                                                                        if (reset)
                                                                        begin
                                                                                ACC = `tcAccLen-1'b1;   // starts at highest value
                                                                                CD = 0;
                                                                                DN = 0;
                                                                        end
                                                                        else
                                                                        begin
                                                                                ACC = ACC - 1'b1;
                                                                                CD = 1'b1;
                                                                                if (ACC < preset)
                                                                                begin
                                                                                        DN = 1'b1;
                                                                                end
                                                                        end
                                                        end
 
 
 
                default         :       begin
                                                        $display ("     error in counter type   ");
                                                        end
 
                endcase
        end
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6	7	maheshpalv	`module counter (clk, reset, preset, type, DN, CU, CD, ACC);`
7
8			`input clk, reset;`
9			input [`tcPresetLen-1:0] preset;
10			input [`tcTypeLen-1:0] type;
11
12			`output DN, CU, CD;`
13			output [`tcAccLen-1:0] ACC;
14
15			`reg DN = 0, CU = 0, CD = 0;`
16			reg [`tcAccLen-1:0] ACC = 0;
17
18			reg [`tcTypeLen-1:0] CounterType;
19			reg [`tcTypeLen-1:0] typeNext;
20
21
22			parameter UpCounter = `tcTypeLen'b01;
23			parameter DownCounter = `tcTypeLen'b10;
24			parameter defaultType = `tcTypeLen'b00;
25
26
27
28			`always @ (type)`
29			`begin`
30
31			`case (type)`
32
33			`counterType1 : begin
34			`typeNext = UpCounter;`
35			`end`
36
37			`counterType2 : begin
38			`typeNext = DownCounter;`
39			`end`
40
41			`default : begin`
42			`$display ("counter is of undefined type.\n Valid types are Up counter & Down counter");`
43			`end`
44			`endcase`
45			`end`
46
47
48			`always @ (posedge clk or posedge reset)`
49			`begin`
50
51			`if (reset)`
52			`begin`
53			`$display ("counter module is reset");`
54			`CounterType = defaultType;`
55			`end`
56			`else`
57			`begin`
58			`CounterType = typeNext;`
59			`end`
60			`end`
61
62
63			`always @ (posedge clk)`
64			`begin`
65
66			`case (CounterType)`
67
68			`UpCounter : begin`
69			`CD = 0; // CD id always 0 for this state`
70
71			`if (reset)`
72			`begin`
73			ACC = `tcAccLen-1'b0; // starts at lowest value
74			`CU = 0;`
75			`DN = 0;`
76			`end`
77			`else`
78			`begin`
79			`ACC = ACC + 1'b1;`
80			`CU = 1'b1;`
81			`if (ACC > preset)`
82			`begin`
83			`DN = 1'b1;`
84			`end`
85			`end`
86			`end`
87
88
89
90			`DownCounter : begin`
91			`CU = 0; // CU id always 0 for this state`
92
93			`if (reset)`
94			`begin`
95			ACC = `tcAccLen-1'b1; // starts at highest value
96			`CD = 0;`
97			`DN = 0;`
98			`end`
99			`else`
100			`begin`
101			`ACC = ACC - 1'b1;`
102			`CD = 1'b1;`
103			`if (ACC < preset)`
104			`begin`
105			`DN = 1'b1;`
106			`end`
107			`end`
108			`end`
109
110
111
112			`default : begin`
113			`$display (" error in counter type ");`
114			`end`
115
116			`endcase`
117			`end`
118
119
120			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [counter_all.v] - Blame information for rev 7