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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [defines.v] - Blame information for rev 10

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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
// 8-bit Pipelined Processor defines
 
`define         immDataLen                      8
 
// program counter & instruction register
`define         instAddrLen                     10                      // 10-bit address => 1024 inst in rom
`define         instLen                         15                      // 15-bit fixed-length instructions
`define         instOpCodeLen           5
`define         instFieldLen            10
 
 
// control unit
`define         cuStateLen                      4               // max 16 states
`define         END                                     `instOpCodeLen'b0
`define         JMP                                     `instOpCodeLen'b1
`define         Ld                                              `instOpCodeLen'b10
`define         Ldi                                     `instOpCodeLen'b11
`define         ST                                              `instOpCodeLen'b100
`define         ADD                                     `instOpCodeLen'b101
`define         SUB                                     `instOpCodeLen'b110
`define         MUL                                     `instOpCodeLen'b111
`define         DIV                                     `instOpCodeLen'b1000
`define         AND                                     `instOpCodeLen'b1001
`define         OR                                              `instOpCodeLen'b1010
`define         XOR                                     `instOpCodeLen'b1011
`define         GrT                                     `instOpCodeLen'b1100
`define         GE                                              `instOpCodeLen'b1101
`define         EQ                                              `instOpCodeLen'b1110
`define         LE                                              `instOpCodeLen'b1111
`define         LT                                              `instOpCodeLen'b10000
`define         PRE                                     `instOpCodeLen'b10001
`define         ETY                                     `instOpCodeLen'b10010
`define         RST                                     `instOpCodeLen'b10011
`define         LdTC                                    `instOpCodeLen'b10100
`define         LdACC                                   `instOpCodeLen'b10101
`define         UARTrd                          `instOpCodeLen'b10110
`define         UARTwr                          `instOpCodeLen'b10111
`define         UARTstat                                `instOpCodeLen'b11000
`define         SPIxFER                         `instOpCodeLen'b11001
`define         SPIstat                         `instOpCodeLen'b11010
`define         SPIwBUF                         `instOpCodeLen'b11011
`define         SPIrBUF                         `instOpCodeLen'b11100
 
// alu opcodes
`define         aluOpcodeLen            4
`define         AND_alu                         `aluOpcodeLen'b0
`define         OR_alu                          `aluOpcodeLen'b1
`define         XOR_alu                         `aluOpcodeLen'b10
`define         GT_alu                          `aluOpcodeLen'b11
`define         GE_alu                          `aluOpcodeLen'b100
`define         EQ_alu                          `aluOpcodeLen'b101
`define         LE_alu                          `aluOpcodeLen'b110
`define         LT_alu                          `aluOpcodeLen'b111
`define         ADD_alu                         `aluOpcodeLen'b1000
`define         SUB_alu                         `aluOpcodeLen'b1001
`define         MUL_alu                         `aluOpcodeLen'b1010
`define         DIV_alu                         `aluOpcodeLen'b1011
`define         LD_data                         `aluOpcodeLen'b1100
 
// bit RAM
`define         bitRamAddrLen           7               // 7-bit address
`define         bitRamDepth                     128     // 2^7 = 128 locations
 
// byte RAM
`define         byteRamLen                      8               // 8-bit input
`define         byteRamAddrLen          7               // 7-bit address
`define         byteRamDepth            128     // 2^7 = 128 locations
 
// input register
`define         inputNumber                     128     // 128 inputs
`define         inputAddrLen            7               // 7-bit address
 
// output register
`define         outputNumber            128     // 128 outputs
`define         outputAddrLen           7               // 7-bit address
 
// accumulator multiplexer
`define         accMuxSelLen                    4               // 2^4 = 16 selections available for accumulator
`define         accMuxSelImmData                `accMuxSelLen'b0
`define         accMuxSelAluOut         `accMuxSelLen'b1
`define         accMuxSelTcLoad         `accMuxSelLen'b10
`define         accMuxSelTcAcc                  `accMuxSelLen'b11
`define         accMuxSelUartData               `accMuxSelLen'b100
`define         accMuxSelUartStat               `accMuxSelLen'b101
`define         accMuxSelSpiStat                `accMuxSelLen'b110
`define         accMuxSelSpiBuf         `accMuxSelLen'b111
 
// operand2 multiplexer
`define         op2MuxSelLen                    4               // 2^4 = 16 selections available for op2
`define         op2MuxSelInput                  `op2MuxSelLen'b0
`define         op2MuxSelOutput         `op2MuxSelLen'b1
`define         op2MuxSelBitRam         `op2MuxSelLen'b10
`define         op2MuxSelByteRam                `op2MuxSelLen'b11
`define         op2MuxSel4                      `op2MuxSelLen'b100
`define         op2MuxSel5                      `op2MuxSelLen'b101
`define         op2MuxSel6                      `op2MuxSelLen'b110
 
//-----------------------------------------------------------------------------------------------------
 
// peripheral defines
`define         timerAndCounter_peripheral
`define         UART_peripheral
`define         SPI_peripheral
 
 
//-----------------------------------------------------------------------------------------------------
 
// Timer-Counter
`define         tcAccLen                                8               // 8-bit accumulated value
`define         tcPresetLen                     8               // 8-bit preset value
`define         tcAddrLen                       4
`define         tcTypeLen                       2               // max 4-types
`define         tcNumbers                       8               // total 8 modules (4-timers, 4-counters)
 
`define         timerType1                      `tcTypeLen'b0
`define         timerType2                      `tcTypeLen'b1
`define         timerType3                      `tcTypeLen'b10
 
`define         counterType1            `tcTypeLen'b1
`define         counterType2            `tcTypeLen'b10
 
 
//-----------------------------------------------------------------------------------------------------
 
// UART
`define         dataBits                        8
`define         sbTick                          16      // ticks for stop bits (16 for 1-stopBit)
`define         fifoWidth                       4
`define                 number_fifo_regs        16
`define                 fifoCntrWidth           5
`define                 fifoDepth                       16

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40	3	maheshpalv
41	8	maheshpalv	`// 8-bit Pipelined Processor defines`
42
43	3	maheshpalv	`define immDataLen 8
44
45			`// program counter & instruction register`
46	7	maheshpalv	`define instAddrLen 10 // 10-bit address => 1024 inst in rom
47	3	maheshpalv	`define instLen 15 // 15-bit fixed-length instructions
48			`define instOpCodeLen 5
49			`define instFieldLen 10
50
51	5	maheshpalv
52			`// control unit`
53			`define cuStateLen 4 // max 16 states
54			`define END `instOpCodeLen'b0
55			`define JMP `instOpCodeLen'b1
56			`define Ld `instOpCodeLen'b10
57			`define Ldi `instOpCodeLen'b11
58			`define ST `instOpCodeLen'b100
59			`define ADD `instOpCodeLen'b101
60			`define SUB `instOpCodeLen'b110
61			`define MUL `instOpCodeLen'b111
62			`define DIV `instOpCodeLen'b1000
63			`define AND `instOpCodeLen'b1001
64			`define OR `instOpCodeLen'b1010
65			`define XOR `instOpCodeLen'b1011
66			`define GrT `instOpCodeLen'b1100
67			`define GE `instOpCodeLen'b1101
68			`define EQ `instOpCodeLen'b1110
69			`define LE `instOpCodeLen'b1111
70			`define LT `instOpCodeLen'b10000
71			`define PRE `instOpCodeLen'b10001
72			`define ETY `instOpCodeLen'b10010
73			`define RST `instOpCodeLen'b10011
74			`define LdTC `instOpCodeLen'b10100
75			`define LdACC `instOpCodeLen'b10101
76			`define UARTrd `instOpCodeLen'b10110
77			`define UARTwr `instOpCodeLen'b10111
78	7	maheshpalv	`define UARTstat `instOpCodeLen'b11000
79			`define SPIxFER `instOpCodeLen'b11001
80			`define SPIstat `instOpCodeLen'b11010
81			`define SPIwBUF `instOpCodeLen'b11011
82			`define SPIrBUF `instOpCodeLen'b11100
83	5	maheshpalv
84	3	maheshpalv	`// alu opcodes`
85			`define aluOpcodeLen 4
86			`define AND_alu `aluOpcodeLen'b0
87			`define OR_alu `aluOpcodeLen'b1
88			`define XOR_alu `aluOpcodeLen'b10
89			`define GT_alu `aluOpcodeLen'b11
90			`define GE_alu `aluOpcodeLen'b100
91			`define EQ_alu `aluOpcodeLen'b101
92			`define LE_alu `aluOpcodeLen'b110
93			`define LT_alu `aluOpcodeLen'b111
94			`define ADD_alu `aluOpcodeLen'b1000
95			`define SUB_alu `aluOpcodeLen'b1001
96			`define MUL_alu `aluOpcodeLen'b1010
97			`define DIV_alu `aluOpcodeLen'b1011
98	5	maheshpalv	`define LD_data `aluOpcodeLen'b1100
99	3	maheshpalv
100			`// bit RAM`
101			`define bitRamAddrLen 7 // 7-bit address
102			`define bitRamDepth 128 // 2^7 = 128 locations
103
104			`// byte RAM`
105			`define byteRamLen 8 // 8-bit input
106			`define byteRamAddrLen 7 // 7-bit address
107			`define byteRamDepth 128 // 2^7 = 128 locations
108
109			`// input register`
110			`define inputNumber 128 // 128 inputs
111			`define inputAddrLen 7 // 7-bit address
112
113			`// output register`
114			`define outputNumber 128 // 128 outputs
115			`define outputAddrLen 7 // 7-bit address
116
117			`// accumulator multiplexer`
118	5	maheshpalv	`define accMuxSelLen 4 // 2^4 = 16 selections available for accumulator
119			`define accMuxSelImmData `accMuxSelLen'b0
120			`define accMuxSelAluOut `accMuxSelLen'b1
121			`define accMuxSelTcLoad `accMuxSelLen'b10
122			`define accMuxSelTcAcc `accMuxSelLen'b11
123	7	maheshpalv	`define accMuxSelUartData `accMuxSelLen'b100
124			`define accMuxSelUartStat `accMuxSelLen'b101
125			`define accMuxSelSpiStat `accMuxSelLen'b110
126			`define accMuxSelSpiBuf `accMuxSelLen'b111
127	3	maheshpalv
128			`// operand2 multiplexer`
129	5	maheshpalv	`define op2MuxSelLen 4 // 2^4 = 16 selections available for op2
130			`define op2MuxSelInput `op2MuxSelLen'b0
131			`define op2MuxSelOutput `op2MuxSelLen'b1
132			`define op2MuxSelBitRam `op2MuxSelLen'b10
133			`define op2MuxSelByteRam `op2MuxSelLen'b11
134	3	maheshpalv	`define op2MuxSel4 `op2MuxSelLen'b100
135			`define op2MuxSel5 `op2MuxSelLen'b101
136			`define op2MuxSel6 `op2MuxSelLen'b110
137
138			`//-----------------------------------------------------------------------------------------------------`
139
140			`// peripheral defines`
141			`define timerAndCounter_peripheral
142			`define UART_peripheral
143	6	maheshpalv	`define SPI_peripheral
144	3	maheshpalv
145
146			`//-----------------------------------------------------------------------------------------------------`
147
148			`// Timer-Counter`
149			`define tcAccLen 8 // 8-bit accumulated value
150			`define tcPresetLen 8 // 8-bit preset value
151			`define tcAddrLen 4
152			`define tcTypeLen 2 // max 4-types
153	7	maheshpalv	`define tcNumbers 8 // total 8 modules (4-timers, 4-counters)
154	3	maheshpalv
155			`define timerType1 `tcTypeLen'b0
156			`define timerType2 `tcTypeLen'b1
157			`define timerType3 `tcTypeLen'b10
158
159			`define counterType1 `tcTypeLen'b1
160			`define counterType2 `tcTypeLen'b10
161
162
163			`//-----------------------------------------------------------------------------------------------------`
164
165			`// UART`
166			`define dataBits 8
167			`define sbTick 16 // ticks for stop bits (16 for 1-stopBit)
168			`define fifoWidth 4
169			`define number_fifo_regs 16
170			`define fifoCntrWidth 5
171			`define fifoDepth 16

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [defines.v] - Blame information for rev 10