URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [inputReg.v] - Blame information for rev 8

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`include "timescale.v"
`include "defines.v"
 
 
 
module inputRegister (reset, inputs, inputRead, inputReadAddr, inputReadOut);
 
        input [`inputNumber-1:0] inputs;
        input inputRead, reset;
        input [`inputAddrLen-1:0] inputReadAddr;
 
        output inputReadOut;
 
        reg inputReadOut;
        reg [`inputNumber-1:0] inputReg;
 
 
        always @ (reset or inputs or inputRead or inputReadAddr)
        begin
 
                if (reset)
                begin
                        inputReadOut = 1'bz;
                        $write ("\nmodule inputRegister is reset        ");
                end
 
                else
                begin
 
                        inputReg = inputs;
 
                        if (inputRead)
                        begin
                                inputReadOut = inputReg [inputReadAddr];
                                $write ("\nreading input        :       module inputRegister    ");
                        end
 
                end
 
        end
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6
7			`module inputRegister (reset, inputs, inputRead, inputReadAddr, inputReadOut);`
8
9			input [`inputNumber-1:0] inputs;
10			`input inputRead, reset;`
11			input [`inputAddrLen-1:0] inputReadAddr;
12
13			`output inputReadOut;`
14
15			`reg inputReadOut;`
16			reg [`inputNumber-1:0] inputReg;
17
18
19			`always @ (reset or inputs or inputRead or inputReadAddr)`
20			`begin`
21
22			`if (reset)`
23			`begin`
24			`inputReadOut = 1'bz;`
25	8	maheshpalv	`$write ("\nmodule inputRegister is reset ");`
26	3	maheshpalv	`end`
27
28			`else`
29			`begin`
30
31			`inputReg = inputs;`
32
33			`if (inputRead)`
34			`begin`
35			`inputReadOut = inputReg [inputReadAddr];`
36	8	maheshpalv	`$write ("\nreading input : module inputRegister ");`
37	3	maheshpalv	`end`
38
39			`end`
40
41			`end`
42
43
44			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [inputReg.v] - Blame information for rev 8