URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [inputReg.v] - Blame information for rev 9

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`include "timescale.v"
`include "defines.v"
 
 
 
module inputRegister (inputs, inputReadAddr, inputReadOut);
 
        input [`inputNumber-1:0] inputs;
        input [`inputAddrLen-1:0] inputReadAddr;
 
        output inputReadOut;
 
        wire [`inputNumber-1:0] inputs;
 
 
 
        assign inputReadOut = inputs[inputReadAddr];
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6
7	9	maheshpalv	`module inputRegister (inputs, inputReadAddr, inputReadOut);`
8	3	maheshpalv
9			input [`inputNumber-1:0] inputs;
10			input [`inputAddrLen-1:0] inputReadAddr;
11
12			`output inputReadOut;`
13
14	9	maheshpalv	wire [`inputNumber-1:0] inputs;
15	3	maheshpalv
16
17
18	9	maheshpalv	`assign inputReadOut = inputs[inputReadAddr];`
19	3	maheshpalv
20
21			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [inputReg.v] - Blame information for rev 9