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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [op2Mux.v] - Blame information for rev 9

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`include "timescale.v"
`include "defines.v"
 
 
module op2Mux (op2MuxSel, inputReadOut, outputReadOut, bitOut, byteOut, op2MuxOut);
 
        input [`op2MuxSelLen-1:0] op2MuxSel;
        input inputReadOut, outputReadOut, bitOut;
        input [7:0] byteOut;
 
        output [7:0] op2MuxOut;
 
        reg [7:0] op2MuxOut = 0;
 
 
        always @ (op2MuxSel)
        begin
 
                case (op2MuxSel)
 
                `op2MuxSelInput :       begin
                                                                op2MuxOut = {7'b0, inputReadOut};
                                                                end
 
                `op2MuxSelOutput        :       begin
                                                                op2MuxOut = {7'b0, outputReadOut};
                                                                end
 
                `op2MuxSelBitRam        :       begin
                                                                op2MuxOut = {7'b0, bitOut};
                                                                end
 
                `op2MuxSelByteRam       :       begin
                                                                op2MuxOut = byteOut;
                                                                end
 
 
                default                 :       begin
                                                                op2MuxOut = op2MuxOut;
                                                                end
 
                endcase
 
        end     // end always
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6			`module op2Mux (op2MuxSel, inputReadOut, outputReadOut, bitOut, byteOut, op2MuxOut);`
7
8			input [`op2MuxSelLen-1:0] op2MuxSel;
9			`input inputReadOut, outputReadOut, bitOut;`
10			`input [7:0] byteOut;`
11
12			`output [7:0] op2MuxOut;`
13
14	9	maheshpalv	`reg [7:0] op2MuxOut = 0;`
15	3	maheshpalv
16
17	9	maheshpalv	`always @ (op2MuxSel)`
18	3	maheshpalv	`begin`
19
20			`case (op2MuxSel)`
21
22	5	maheshpalv	`op2MuxSelInput : begin
23	3	maheshpalv	`op2MuxOut = {7'b0, inputReadOut};`
24			`end`
25
26	5	maheshpalv	`op2MuxSelOutput : begin
27	3	maheshpalv	`op2MuxOut = {7'b0, outputReadOut};`
28			`end`
29
30	5	maheshpalv	`op2MuxSelBitRam : begin
31	3	maheshpalv	`op2MuxOut = {7'b0, bitOut};`
32			`end`
33
34	5	maheshpalv	`op2MuxSelByteRam : begin
35	3	maheshpalv	`op2MuxOut = byteOut;`
36			`end`
37
38
39			`default : begin`
40	9	maheshpalv	`op2MuxOut = op2MuxOut;`
41	3	maheshpalv	`end`
42
43			`endcase`
44
45			`end // end always`
46
47
48			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [op2Mux.v] - Blame information for rev 9