Subversion Repositories instruction_list_pipelined_processor_with_peripherals

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////    This file is part of the project                                                                                        ////

////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////

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////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////

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////                             Author:                                                                                ////

////                            - Mahesh Sukhdeo Palve                                                                                                  ////

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////                                    This source file may be used and distributed without                    ////

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////                                    This source file is free software; you can redistribute it              ////

////                                    and/or modify it under the terms of the GNU Lesser General              ////

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`include "timescale.v"

`include "defines.v"

module outputReg (reset, outputRw, outputRwAddr, outputWriteIn, outputReadOut, outputs);

        input reset, outputRw;

        input [`outputAddrLen-1:0] outputRwAddr;

        input outputWriteIn;

        output outputReadOut;

        output [`outputNumber-1:0] outputs;

        reg outputReadOut;

        reg [`outputNumber-1:0] outputs = 0;

        reg [`outputNumber-1 :0] outputReg = 0;

        always @ (reset or outputRw or outputRwAddr or outputWriteIn or outputReg)

        begin

                if (reset)

                begin

                        outputReadOut = 1'bz;

                        $write ("\nmodule outputRegister is reset       ");

                end

                else

                begin

                        outputs = outputReg;

                        if (outputRw)   // read output status

                        begin

                                outputReadOut = outputReg[outputRwAddr];

//                              $write ("\nreading output register      :       module outputRegister   ");

                        end

                        else                            // write operation

                        begin

                                outputReg[outputRwAddr] = outputWriteIn;

//                              $write ("\nwriting to the output register       :       module outputRegister   ");

                        end

                end

        end

endmodule