URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ppReg1.v] - Blame information for rev 6

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`include "timescale.v"
`include "defines.v"
 
 
module ppReg1 (clk, opcodeIn, fieldIn, opcodeOut, fieldOut);
 
                input clk;
                input [`instOpCodeLen-1:0] opcodeIn;
                input [`instFieldLen-1:0] fieldIn;
 
                output [`instOpCodeLen-1:0] opcodeOut;
                output [`instFieldLen-1:0] fieldOut;
 
                reg [`instOpCodeLen-1:0] opcodeOut;
                reg [`instFieldLen-1:0] fieldOut;
 
 
                always @ (posedge clk)
                begin
 
                                opcodeOut = opcodeIn;
                                fieldOut = fieldIn;
                end
 
 
 
endmodule

Line No.	Rev	Author	Line
1	6	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6			`module ppReg1 (clk, opcodeIn, fieldIn, opcodeOut, fieldOut);`
7
8			`input clk;`
9			input [`instOpCodeLen-1:0] opcodeIn;
10			input [`instFieldLen-1:0] fieldIn;
11
12			output [`instOpCodeLen-1:0] opcodeOut;
13			output [`instFieldLen-1:0] fieldOut;
14
15			reg [`instOpCodeLen-1:0] opcodeOut;
16			reg [`instFieldLen-1:0] fieldOut;
17
18
19			`always @ (posedge clk)`
20			`begin`
21
22			`opcodeOut = opcodeIn;`
23			`fieldOut = fieldIn;`
24			`end`
25
26
27
28			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ppReg1.v] - Blame information for rev 6