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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ppReg2.v] - Blame information for rev 12

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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
 
module ppReg2 (clk,
                                        accMuxSelIn, accEnIn, op2MuxSelIn, aluEnIn, aluOpcodeIn,
                                        bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn,
                                        outputRwIn
 
                                        `ifdef timerAndCounter_peripheral
                                                , entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn
                                        `endif
 
                                        `ifdef UART_peripheral
                                                , uartReadIn, uartWriteIn
                                        `endif
 
                                        , fieldIn
                                        , accMuxSelOut, accEnOut, op2MuxSelOut, aluEnOut, aluOpcodeOut,
                                        bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
                                        outputRwOut
 
                                        `ifdef timerAndCounter_peripheral
                                                , entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut
                                        `endif
 
                                        `ifdef UART_peripheral
                                                , uartReadOut, uartWriteOut
                                        `endif
 
                                        , fieldOut
                                        );
 
        input clk;
 
        input [`accMuxSelLen-1:0]        accMuxSelIn;
        input accEnIn;
        input [`op2MuxSelLen-1:0]        op2MuxSelIn;
        input aluEnIn;
        input [`aluOpcodeLen-1:0] aluOpcodeIn;
        input bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn;
        input outputRwIn;
        `ifdef timerAndCounter_peripheral
        input entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn;
        `endif
        `ifdef UART_peripheral
        input uartReadIn, uartWriteIn;
        `endif
        input [`instFieldLen-1:0] fieldIn;
 
 
        output [`accMuxSelLen-1:0]       accMuxSelOut;
        output accEnOut;
        output [`op2MuxSelLen-1:0]       op2MuxSelOut;
        output aluEnOut;
        output [`aluOpcodeLen-1:0] aluOpcodeOut;
        output bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
        output outputRwOut;
        `ifdef timerAndCounter_peripheral
        output entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;
        `endif
        `ifdef UART_peripheral
        output uartReadOut, uartWriteOut;
        `endif
 
        output [`instFieldLen-1:0] fieldOut;
 
        reg [`accMuxSelLen-1:0]  accMuxSelOut;
        reg accEnOut;
        reg [`op2MuxSelLen-1:0]  op2MuxSelOut;
        reg aluEnOut;
        reg [`aluOpcodeLen-1:0] aluOpcodeOut;
        reg bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
        reg outputRwOut;
        `ifdef timerAndCounter_peripheral
        reg entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;
        `endif
        `ifdef UART_peripheral
        reg uartReadOut, uartWriteOut;
        `endif
 
        reg [`instFieldLen-1:0] fieldOut;
 
 
 
        always @ (posedge clk)
        begin
 
        fieldOut = fieldIn;
 
        accMuxSelOut = accMuxSelIn;
        accEnOut = accEnIn;
        op2MuxSelOut = op2MuxSelIn;
        aluEnOut = aluEnIn;
        aluOpcodeOut = aluOpcodeIn;
        bitRamEnOut = bitRamEnIn;
        bitRamRwOut = bitRamRwIn;
        byteRamEnOut = byteRamEnIn;
        byteRamRwOut = byteRamRwIn;
        outputRwOut = outputRwIn;
 
        `ifdef timerAndCounter_peripheral
 
        entypeEnOut = entypeEnIn;
        tcAccReadOut = tcAccReadIn;
        tcResetEnOut = tcResetEnIn;
        tcPresetEnOut = tcPresetEnIn;
 
        `endif
 
 
        `ifdef UART_peripheral
 
        uartReadOut = uartReadIn;
        uartWriteOut = uartWriteIn;
 
        `endif
 
 
        end
 
 
endmodule

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40	6	maheshpalv
41			`include "timescale.v"
42			`include "defines.v"
43
44
45			`module ppReg2 (clk,`
46			`accMuxSelIn, accEnIn, op2MuxSelIn, aluEnIn, aluOpcodeIn,`
47			`bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn,`
48	12	maheshpalv	`outputRwIn`
49	6	maheshpalv
50			`ifdef timerAndCounter_peripheral
51	12	maheshpalv	`, entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn`
52	6	maheshpalv	`endif
53
54			`ifdef UART_peripheral
55			`, uartReadIn, uartWriteIn`
56			`endif
57
58			`, fieldIn`
59	12	maheshpalv	`, accMuxSelOut, accEnOut, op2MuxSelOut, aluEnOut, aluOpcodeOut,`
60	6	maheshpalv	`bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,`
61	12	maheshpalv	`outputRwOut`
62	6	maheshpalv
63			`ifdef timerAndCounter_peripheral
64	12	maheshpalv	`, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut`
65	6	maheshpalv	`endif
66
67			`ifdef UART_peripheral
68			`, uartReadOut, uartWriteOut`
69			`endif
70
71			`, fieldOut`
72			`);`
73
74			`input clk;`
75
76			input [`accMuxSelLen-1:0] accMuxSelIn;
77			`input accEnIn;`
78			input [`op2MuxSelLen-1:0] op2MuxSelIn;
79			`input aluEnIn;`
80			input [`aluOpcodeLen-1:0] aluOpcodeIn;
81			`input bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn;`
82	12	maheshpalv	`input outputRwIn;`
83	6	maheshpalv	`ifdef timerAndCounter_peripheral
84	12	maheshpalv	`input entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn;`
85	6	maheshpalv	`endif
86			`ifdef UART_peripheral
87			`input uartReadIn, uartWriteIn;`
88			`endif
89			input [`instFieldLen-1:0] fieldIn;
90
91
92			output [`accMuxSelLen-1:0] accMuxSelOut;
93			`output accEnOut;`
94			output [`op2MuxSelLen-1:0] op2MuxSelOut;
95			`output aluEnOut;`
96			output [`aluOpcodeLen-1:0] aluOpcodeOut;
97			`output bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;`
98	12	maheshpalv	`output outputRwOut;`
99	6	maheshpalv	`ifdef timerAndCounter_peripheral
100	12	maheshpalv	`output entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;`
101	6	maheshpalv	`endif
102			`ifdef UART_peripheral
103			`output uartReadOut, uartWriteOut;`
104			`endif
105
106			output [`instFieldLen-1:0] fieldOut;
107
108			reg [`accMuxSelLen-1:0] accMuxSelOut;
109			`reg accEnOut;`
110			reg [`op2MuxSelLen-1:0] op2MuxSelOut;
111			`reg aluEnOut;`
112			reg [`aluOpcodeLen-1:0] aluOpcodeOut;
113			`reg bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;`
114	12	maheshpalv	`reg outputRwOut;`
115	6	maheshpalv	`ifdef timerAndCounter_peripheral
116	12	maheshpalv	`reg entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;`
117	6	maheshpalv	`endif
118			`ifdef UART_peripheral
119			`reg uartReadOut, uartWriteOut;`
120			`endif
121
122			reg [`instFieldLen-1:0] fieldOut;
123
124
125
126			`always @ (posedge clk)`
127			`begin`
128
129			`fieldOut = fieldIn;`
130
131			`accMuxSelOut = accMuxSelIn;`
132			`accEnOut = accEnIn;`
133			`op2MuxSelOut = op2MuxSelIn;`
134			`aluEnOut = aluEnIn;`
135			`aluOpcodeOut = aluOpcodeIn;`
136			`bitRamEnOut = bitRamEnIn;`
137			`bitRamRwOut = bitRamRwIn;`
138			`byteRamEnOut = byteRamEnIn;`
139			`byteRamRwOut = byteRamRwIn;`
140			`outputRwOut = outputRwIn;`
141
142			`ifdef timerAndCounter_peripheral
143
144			`entypeEnOut = entypeEnIn;`
145			`tcAccReadOut = tcAccReadIn;`
146			`tcResetEnOut = tcResetEnIn;`
147			`tcPresetEnOut = tcPresetEnIn;`
148	12	maheshpalv
149	6	maheshpalv	`endif
150
151
152			`ifdef UART_peripheral
153
154			`uartReadOut = uartReadIn;`
155			`uartWriteOut = uartWriteIn;`
156
157			`endif
158
159
160			`end`
161
162
163			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ppReg2.v] - Blame information for rev 12