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maheshpalv |
////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the project ////
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//// "instruction_list_pipelined_processor_with_peripherals" ////
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//// ////
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//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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//// ////
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//// ////
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//// Author: ////
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//// - Mahesh Sukhdeo Palve ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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6 |
maheshpalv |
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`include "timescale.v"
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`include "defines.v"
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module ppReg2 (clk,
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branchIn,
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accMuxSelIn, accEnIn, op2MuxSelIn, aluEnIn, aluOpcodeIn,
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bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn,
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inputReadIn, outputRwIn
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`ifdef timerAndCounter_peripheral
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, entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn, tcLoadEnIn
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`endif
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`ifdef UART_peripheral
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, uartReadIn, uartWriteIn
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`endif
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`ifdef SPI_peripheral
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, sconEnIn, spiStatReadIn, spiBufReadIn, spiBufWriteIn, spiBufShiftIn
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`endif
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, fieldIn
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, branchOut,
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accMuxSelOut, accEnOut, op2MuxSelOut, aluEnOut, aluOpcodeOut,
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bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
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inputReadOut, outputRwOut
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`ifdef timerAndCounter_peripheral
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, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
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`endif
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`ifdef UART_peripheral
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, uartReadOut, uartWriteOut
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`endif
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`ifdef SPI_peripheral
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, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
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`endif
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, fieldOut
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);
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input clk;
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input branchIn;
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input [`accMuxSelLen-1:0] accMuxSelIn;
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input accEnIn;
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input [`op2MuxSelLen-1:0] op2MuxSelIn;
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input aluEnIn;
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input [`aluOpcodeLen-1:0] aluOpcodeIn;
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input bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn;
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input inputReadIn, outputRwIn;
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`ifdef timerAndCounter_peripheral
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input entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn, tcLoadEnIn;
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`endif
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`ifdef UART_peripheral
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input uartReadIn, uartWriteIn;
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`endif
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`ifdef SPI_peripheral
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input sconEnIn, spiStatReadIn, spiBufReadIn, spiBufWriteIn, spiBufShiftIn;
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`endif
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input [`instFieldLen-1:0] fieldIn;
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output branchOut;
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output [`accMuxSelLen-1:0] accMuxSelOut;
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output accEnOut;
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output [`op2MuxSelLen-1:0] op2MuxSelOut;
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output aluEnOut;
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output [`aluOpcodeLen-1:0] aluOpcodeOut;
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output bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
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output inputReadOut, outputRwOut;
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`ifdef timerAndCounter_peripheral
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output entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
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`endif
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`ifdef UART_peripheral
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output uartReadOut, uartWriteOut;
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`endif
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`ifdef SPI_peripheral
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output sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
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`endif
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output [`instFieldLen-1:0] fieldOut;
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reg branchOut;
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reg [`accMuxSelLen-1:0] accMuxSelOut;
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reg accEnOut;
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reg [`op2MuxSelLen-1:0] op2MuxSelOut;
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reg aluEnOut;
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reg [`aluOpcodeLen-1:0] aluOpcodeOut;
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reg bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
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reg inputReadOut, outputRwOut;
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`ifdef timerAndCounter_peripheral
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reg entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
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`endif
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`ifdef UART_peripheral
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reg uartReadOut, uartWriteOut;
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`endif
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`ifdef SPI_peripheral
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reg sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
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`endif
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reg [`instFieldLen-1:0] fieldOut;
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always @ (posedge clk)
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begin
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fieldOut = fieldIn;
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branchOut = branchIn;
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accMuxSelOut = accMuxSelIn;
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accEnOut = accEnIn;
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op2MuxSelOut = op2MuxSelIn;
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aluEnOut = aluEnIn;
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aluOpcodeOut = aluOpcodeIn;
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bitRamEnOut = bitRamEnIn;
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bitRamRwOut = bitRamRwIn;
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byteRamEnOut = byteRamEnIn;
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byteRamRwOut = byteRamRwIn;
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inputReadOut = inputReadIn;
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outputRwOut = outputRwIn;
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`ifdef timerAndCounter_peripheral
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entypeEnOut = entypeEnIn;
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tcAccReadOut = tcAccReadIn;
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tcResetEnOut = tcResetEnIn;
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tcPresetEnOut = tcPresetEnIn;
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tcLoadEnOut = tcLoadEnIn;
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`endif
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`ifdef UART_peripheral
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uartReadOut = uartReadIn;
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uartWriteOut = uartWriteIn;
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`endif
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`ifdef SPI_peripheral
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sconEnOut = sconEnIn;
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spiStatReadOut = spiStatReadIn;
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spiBufReadOut = spiBufReadIn;
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spiBufWriteOut = spiBufWriteIn;
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spiBufShiftOut = spiBufShiftIn;
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`endif
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end
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endmodule
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