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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ramBit.v] - Blame information for rev 8

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`include "timescale.v"
`include "defines.v"
 
module bitRam (clk, reset, bitRamEn, bitRamRw, bitRamIn, bitRamAddr, bitRamOut);
 
 
                input   clk, reset, bitRamEn, bitRamRw, bitRamIn;
                input [`bitRamAddrLen-1:0]       bitRamAddr;
 
                output bitRamOut;
 
                reg bitRam [`bitRamDepth-1:0];
                reg bitRamOut;
 
 
                always @ (posedge clk or posedge reset)
                begin
 
                        if (reset)
                        begin
                                bitRamOut = 1'b0;
                                $write ("\nmodule bitRam is reset       ");
                        end
 
                        else
                        begin
 
                        if (bitRamEn)
                        begin
                                if (bitRamRw)   // read operation
                                begin
                                        bitRamOut = bitRam[bitRamAddr];
//                                      $write ("\nreading bit-RAM      :       module bitRAM   ");
                                end
 
                                else                            // write operation
                                begin
                                        bitRam[bitRamAddr] = bitRamIn;
//                                      $write ("\nwriting to bit-RAM   :       module bitRam   ");
                                end
                        end
 
                        else
                        begin
                                bitRamOut = 1'bZ;
                        end
 
                        end     // end else of reset
 
                end     // end always block
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5			`module bitRam (clk, reset, bitRamEn, bitRamRw, bitRamIn, bitRamAddr, bitRamOut);`
6
7
8			`input clk, reset, bitRamEn, bitRamRw, bitRamIn;`
9			input [`bitRamAddrLen-1:0] bitRamAddr;
10
11			`output bitRamOut;`
12
13			reg bitRam [`bitRamDepth-1:0];
14			`reg bitRamOut;`
15
16
17			`always @ (posedge clk or posedge reset)`
18			`begin`
19
20			`if (reset)`
21			`begin`
22			`bitRamOut = 1'b0;`
23	8	maheshpalv	`$write ("\nmodule bitRam is reset ");`
24	3	maheshpalv	`end`
25
26			`else`
27			`begin`
28
29			`if (bitRamEn)`
30			`begin`
31			`if (bitRamRw) // read operation`
32			`begin`
33			`bitRamOut = bitRam[bitRamAddr];`
34	8	maheshpalv	`// $write ("\nreading bit-RAM : module bitRAM ");`
35	3	maheshpalv	`end`
36
37			`else // write operation`
38			`begin`
39			`bitRam[bitRamAddr] = bitRamIn;`
40	8	maheshpalv	`// $write ("\nwriting to bit-RAM : module bitRam ");`
41	3	maheshpalv	`end`
42			`end`
43
44			`else`
45			`begin`
46			`bitRamOut = 1'bZ;`
47			`end`
48
49			`end // end else of reset`
50
51			`end // end always block`
52
53
54			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ramBit.v] - Blame information for rev 8