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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ramByte.v] - Blame information for rev 8

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`include "timescale.v"
`include "defines.v"
 
module byteRam (clk, reset, byteRamEn, byteRamRw, byteRamIn, byteRamAddr, byteRamOut);
 
                input clk, reset, byteRamEn, byteRamRw;
                input [`byteRamLen-1:0] byteRamIn;
                input [`byteRamAddrLen-1:0] byteRamAddr;
 
                output [`byteRamLen-1:0] byteRamOut;
 
                reg [`byteRamLen-1:0] byteRam [`byteRamDepth-1:0];
                reg [`byteRamLen-1:0] byteRamOut;
 
 
                always @ (posedge clk or posedge reset)
                begin
 
                        if (reset)
                        begin
                                byteRamOut = `byteRamLen'b0;
                                $write ("\nmodule byteRam is reset      ");
                        end
 
                        else
                        begin
 
                        if (byteRamEn)
                        begin
 
                                if (byteRamRw)          // read operation
                                begin
                                        byteRamOut = byteRam[byteRamAddr];
//                                      $write ("\nreading byte RAM : module byteRam    ");
                                end
 
 
                                else                                    // write operation
                                begin
                                        byteRam[byteRamAddr] = byteRamIn;
//                                      $write ("\nwriting to byte RAM  :       module byteRam  ");
                                end
 
                        end
 
                        else                    // if Enable = 0
                        begin
 
                                byteRamOut = `byteRamLen'bz;
 
                        end
 
                        end             // end else of reset
 
                end     // end always
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5			`module byteRam (clk, reset, byteRamEn, byteRamRw, byteRamIn, byteRamAddr, byteRamOut);`
6
7			`input clk, reset, byteRamEn, byteRamRw;`
8			input [`byteRamLen-1:0] byteRamIn;
9			input [`byteRamAddrLen-1:0] byteRamAddr;
10
11			output [`byteRamLen-1:0] byteRamOut;
12
13			reg [`byteRamLen-1:0] byteRam [`byteRamDepth-1:0];
14			reg [`byteRamLen-1:0] byteRamOut;
15
16
17			`always @ (posedge clk or posedge reset)`
18			`begin`
19
20			`if (reset)`
21			`begin`
22			byteRamOut = `byteRamLen'b0;
23	8	maheshpalv	`$write ("\nmodule byteRam is reset ");`
24	3	maheshpalv	`end`
25
26			`else`
27			`begin`
28
29			`if (byteRamEn)`
30			`begin`
31
32			`if (byteRamRw) // read operation`
33			`begin`
34			`byteRamOut = byteRam[byteRamAddr];`
35	8	maheshpalv	`// $write ("\nreading byte RAM : module byteRam ");`
36	3	maheshpalv	`end`
37
38
39			`else // write operation`
40			`begin`
41			`byteRam[byteRamAddr] = byteRamIn;`
42	8	maheshpalv	`// $write ("\nwriting to byte RAM : module byteRam ");`
43	3	maheshpalv	`end`
44
45			`end`
46
47			`else // if Enable = 0`
48			`begin`
49
50			byteRamOut = `byteRamLen'bz;
51
52			`end`
53
54			`end // end else of reset`
55
56			`end // end always`
57
58			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ramByte.v] - Blame information for rev 8