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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [tcLoad.v] - Blame information for rev 10

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1 10 maheshpalv
////////////////////////////////////////////////////////////////////////////////////////////////
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////                                                                                                                    ////
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////                                                                                                                    ////
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////    This file is part of the project                                                                                        ////
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////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
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////                                                                                                                    ////
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////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
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////                                                                                                                    ////
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////                                                                                                                    ////
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////                             Author:                                                                                ////
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////                            - Mahesh Sukhdeo Palve                                                                                                  ////
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////                                                                                                                                                                            ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////                                                                                                                                                                            ////
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////                                                                                                                                                            ////
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////                                                                                                                    ////
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////                                    This source file may be used and distributed without                    ////
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////                                    restriction provided that this copyright statement is not               ////
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////                                    removed from the file and that any derivative work contains             ////
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////                                    the original copyright notice and the associated disclaimer.            ////
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////                                                                                                                    ////
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////                                    This source file is free software; you can redistribute it              ////
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////                                    and/or modify it under the terms of the GNU Lesser General              ////
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////                                    Public License as published by the Free Software Foundation;            ////
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////                                    either version 2.1 of the License, or (at your option) any              ////
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////                                    later version.                                                          ////
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////                                                                                                                    ////
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////                                    This source is distributed in the hope that it will be                  ////
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////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
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////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
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////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
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////                                    details.                                                                ////
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////                                                                                                                    ////
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////                                    You should have received a copy of the GNU Lesser General               ////
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////                                    Public License along with this source; if not, download it              ////
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////                                    from http://www.opencores.org/lgpl.shtml                                ////
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////                                                                                                                    ////
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////////////////////////////////////////////////////////////////////////////////////////////////
40 3 maheshpalv
 
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`include "timescale.v"
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`include "defines.v"
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module tcLoad (tcLoadEn, tcAddr, dnIn, ttIn, cuIn, cdIn, tcLoadOut);
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        input tcLoadEn;
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        input [`tcAddrLen-1:0] tcAddr;
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        input [`tcNumbers-1:0] dnIn, ttIn, cuIn, cdIn;
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        output [7:0] tcLoadOut;
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        reg [`tcNumbers-1:0] dnInReg, ttInReg, cuInReg, cdInReg;
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        wire dnSel, ttSel, cuSel, cdSel;
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        always @ *
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        begin
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                dnInReg = dnIn;
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                ttInReg = ttIn;
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                cuInReg = cuIn;
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                cdInReg = cdIn;
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        end
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        assign dnSel = dnInReg[tcAddr];
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        assign ttSel = ttInReg[tcAddr];
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        assign cuSel = cuInReg[tcAddr];
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        assign cdSel = cdInReg[tcAddr];
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        assign tcLoadOut = {4'b0, dnSel, ttSel, cuSel, cdSel};
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endmodule

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